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wishbone
wishbone接口的设计,在交换机和MAC之间建立wishbone接口(the wishbone interface design, wishbone interface between the switch and MAC)
- 2012-12-05 12:22:24下载
- 积分:1
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USB转RS232
USB转RS232RSTTLRS485FT232+SP213串口的原理图AD画的(USB to RS232RSTTLRS485FT232+SP213 serial port schematic AD drawing)
- 2020-07-01 04:20:02下载
- 积分:1
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verilog_lab_solution
Verilog 实验代码。。。经典的,里面都是完整的项目文件。 ISE环境。(Verilog test code. . . Classic, which is a complete project file. ISE environment.)
- 2011-12-01 23:44:40下载
- 积分:1
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AD9250 204b Verilog源码
说明: AD9250是一款双通道14位ADC,最高采样速率250 MSPS,JESD204B Subclass 0或Subclass 1编码串行数字输出(The ad9250 is a dual channel 14 bit ADC with a maximum sampling rate of 250 MSPs and jesd204b sub class 0 or sub class 1 coded serial digital output)
- 2021-04-14 11:01:55下载
- 积分:1
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formal_verification
说明: 现在最流行的RTL设计方法之一,本书为全球流行的设计入门书籍(One of the most popular RTL design methods nowadays, this book is an introductory book for popular design all over the world.)
- 2020-06-23 22:00:02下载
- 积分:1
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ADC-Parameter
外部ADC采集数据,存为数组文件。通过程序读入,然后即可求出ADC的SNR、SINAD、THD、ENOB等。(External ADC data collection, stored as an array of documents. Read through the program, then the ADC SNR, SINAD, THD, ENOB can be calculated.)
- 2021-03-15 21:39:22下载
- 积分:1
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generic_dpram
IT IS THE DP MEMORY MODULE. IT CONTROLS THE DP MEMORY
- 2013-09-30 19:03:40下载
- 积分:1
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Noc
credit base network on chip(network on chip (noc))
- 2020-06-19 11:40:02下载
- 积分:1
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在USB contreoller CRC5块
crc5 bolck in usb contreoller
- 2022-03-06 23:01:25下载
- 积分:1
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Nexys-4-DDR-XADC
Nexys-4-DDR-XADC 开发板demo(Nexys-4-DDR-XADC e.v. Board demo)
- 2018-12-07 15:33:22下载
- 积分:1