VHDL实现的读取和写入SDRAM的程序代码，学习的人可以参考下

这是可编程逻辑器件（CPLD）初学者的入门级文章，仅供参考。-This is the programmable logic device (CPLD), the entry-level beginners articles for reference purposes only.

PCI IP 核 Xilinx原版，很好用，国际知名公司Xilinx原版，值得信赖

用verilog编写的分辨率提高的源代码 采用双线性插值(Written resolution with the verilog source code to improve the use of bilinear interpolation)

FPGA课程设计源码，整合VGA,PS2键盘，CORDIC三角函数算法，在basys2平台上使用完全可行。(FPGA curriculum design source, integrated VGA, PS2 keyboard, CORDIC trigonometric algorithm, used on basys2 platform entirely feasible.)

说明：  RISC全部源码，包含仿真文件，使用makefile脚本编写，能通过vcs编译(RISC all source code, including simulation files, using makefile script, can be compiled through VCS)

千兆以太网设计，包括组包解包，可以实现大数据传输功能。(Unpack the gigabit Ethernet is designed, including group package, can realize large data transfer function.)

数字钟(Digital clock)

Srikanth Vijayaraghavan - A Practical Guide for SystemVerilog Assertions-Srikanth Vijayaraghavan- A Practical Guide for SystemVerilog Assertions

attachement of attachments..bits pilani

在FPGA上实现CAN总线SPI接口通信，使用Verilog语言(Realize SPI interface communication of CAN bus on FPGA, using Verilog language)