芦苇

TD-LTE中（3.1.7）咬尾卷积码编码器verilog代码(Tail-biting convolutional code encoder verilog code)

一个FIR低通滤波器,最小阻带衰减-30db,带内波动小于1db．用MAXPLUS2设计与仿真。-This is a FIR LPF, with-30dB in stop-band and sigma is less than 1dB. It is designed and simulated on MAXPLUS2.

io 组件，用vhdl实现io端口的控制，包括输入输出，握手信号，-io port VHDL code

一些较为经典的VHDL代码,专注于信号分析与检测方面-Some of the more classic of the VHDL code, focusing on signal analysis and testing

CMV2000的对齐模块，适用于其他对齐模块，自行修改(CMV2000 alignment module, suitable for other alignment modules, self-modifying)

这是在 vhdl 的简单循环的拳头在后进先出队列。缓冲区的大小和数据大小可以通过 N 和 W 的参数配置。队列最前面的是可用输出数据。两个信号控制写入和读取数据。如果缓冲区是空的还是满的两个输出信号信息。

实用的程序代码，希望对大家有用，已经调试通过-Practical program code, in the hope that useful to everybody, has debugging through

本程序使用Verilog语言实现了SPI接口的设计，可以直接烧到FPGA实现与MCU的通信,自带有测试文件。(The program uses the Verilog language design SPI interface, you can burn directly communicate with the FPGA, MCU, comes with a test file.)

GPIO LED 测试工具源代码，可以用来检测开发的主板GPIO LED设备是否工作正常(GPIO LED test tool source code, can be used to detect the development of motherboard GPIO LED device is working properly)

VHDL implementation of RC6 encryption algorithm Test file represent applying all zero input and all zero key note that result is correct but bytes positions are swapped