说明：  基于FPGA的液晶显示控制器的设计，FPGA用的是EP2C5,LCD用的是ST7920内核的122*32点阵的LCD，显示中西文字符(FPGA-based LCD display controller design, FPGA is used EP2C5, LCD is used in the ST7920 core of 122* 32 dot matrix LCD, display of Chinese and Western characters)

this a vhdl code for usb-this is a vhdl code for usb

M25P64-SPI-FLASH芯片的FPGA控制程序，已仿真验证(M25P64- SPI- FLASH chip FPGA control program, simulation)

vhdl编的dds函数发生器，完成sin(x)曲线的生成-vhdl function generator dds compiled to complete the sin (x) curve is generated

说明：  掌握SDRAM数据读写、刷新、初始化以及FPGA串口收发时序，熟练FIFO IP核的生成和调用。(Master SDRAM data read and write, refresh, initialization and the timing of sending and receiving of the serial port of the FPGA, skilled in the generation and invocation of the FIFO IP core.)

实现与电脑端串行数据发送与接收，波特率为9600(Realize serial data sending and receiving with the computer terminal)

TEXIO study testbench passed VHDL FPGA CPLD simulation Altera quartus

用verilog hdl写的Norflash控制器，可实现单字节读写，扇区擦除。(Norflash controller edit by Verilog hdl,it can read or write by Byte,or erase the sector.)

ISE 9.2 serials working

The objective of this project is to design and implement the controller for an electronic safe. You will interface a 16-button keypad to the NIOS boards. The combination code of the safe will be the last