Realize with a clock input, can realize multi

针对传统CPM正交扩频系统实现复杂度高的问题，提出了一种基于预编码的CPM正交扩频系统。(Pre—encoded CPM orthogonal spread spectrum system)

数字信号源，输出不同频率，相位的正余弦信号，-Digital signal source, the output of different frequency, phase is the cosine signal,

FPGA实现乒乓球游戏 代码及仿真 VGA实现(FPGA realizes table tennis game code and simulation VGA implementation)

100个VHDL的例子-100 examples of VHDL

Verilog UART is written in this file

四位乘法器的VHDL源程序-four Multiplier VHDL source

一个简单的uvm搭建的ahb简单实例,包含了各个组件以及编译的运行的脚本(one sample example about ahb，include every component and compile script)

说明：  这个事VHDL基础知识，内面主要内容是编码器的插V过程，值得下载学习！(it is really useful for those who never touch it!)

十一和通过vivado实现多周期cpu，各种作业再里面包含了(Realizing multi period CPU)

该工程用verilog编写，已通过串口调试助手调试通过，接收模块采采用8倍波特率采样数据，有较好的滤波功能，在PC上完成自发自收功能。 (The project is written in verilog debugging through serial debugging assistant, adopted 8 times the baud rate sampling data receiver module, better filtering done on the PC spontaneous self-closing function.)