The VHDL source code digital clock, you can achieve at school, school grade feat...

UART的完整发送程序，包括完整的工程核源代码。-UART to send the complete procedure, including the complete source code of nuclear engineering.

用Verilog 实现的电子时钟，给初学者一个模版，学习Verilog。-Using Verilog realize an electronic clock, a template for beginners to learn Verilog.

两篇中文论文，详细叙述了Farrow滤波器的设计方式和理论基础，非常实用！(Two Chinese papers, described in detail Farrow filter design methods and theoretical foundation, very useful!)

DESCRIPTION OF FULL ADDER

this is code verilog

VHDL语言写的波形发生器和sine波形发生器,一共两个文件，通信开发平台专用。这是一个典型的正玄波发生器程序和一个任意波形发生器程序，大家可以参考学习，对于vhdl入门还是很有帮助的-This is a typical wave generator Shogen procedures and an arbitrary waveform generator procedures, Members can take a learning portal for VHDL or helpful

fpga的按键程序，实现按键和led的对应点亮。(The key program of FPGA realizes the corresponding lighting between keys and led.)

FPGA代码，包含地址译码模块、16位锁存器、AD片选、死区及滤除窄脉冲、过流和短路保护、解除脉冲封锁模块、PWM模块、PWM选择 (FPGA code, including the address decoder module 16 latches, AD chip select, filter out the dead and narrow pulse, overcurrent and short circuit protection, lifting the blockade pulse module, PWM module, PWM selection)

存储示波器，功能齐全通过验证，毕业设计用-Storage oscilloscope, a full-featured validated, graduation design

quick reference guide to verilog HDL