The VHDL source code digital clock, you can achieve at school, school grade feat...

本练习的目的是构建和使用计数器。所设计的电路将在计算机上实现

周立功Fusion StartKit，fpga开发板的实验例程，Flash Memory初始化RAM实验(ZLG Fusion StartKit, fpga development board test routines Flash Memory Initialize RAM experiments)

ISE 9.2 serials working

16位并行乘法器源代码，booth2编码，二进制树拓扑结构(16bits parallel multiplier source code )

三种方法编写多路选择器的VHDL源代码 分别使用if else ,select ,when 语句-three methods to prepare multiple choice of VHDL source code were used if else, select, when words

OFDM系统新型CC编解码的verilogHDL设计，与RS编码级联，经测试误码率性能提高(OFDM system verilogHDL new CC codec design, coding and RS cascade, tested BER performance improvement)

在ＶＨＤＬ上编写了UART通信协议，对于ＦＰＧＡ开发有很大帮助-In VHDL on the preparation of a UART communication protocol, for FPGA development of great help

一个用VerilogHDL语言编写的8X8的乘法器-a Verilog HDL language used in the preparation of the multiplier 8X8

主控cc2530通过debug接口对目标cc2530进行程序烧写，使用DMA进行数据传输，已调试通过。(Master cc2530 through the debug interface for writing the program to target cc2530, using the DMA data transfer, has been work successful.)

LCD图形显示代码，已调试过，可以运行成功(LCD graphics display code has been debugged, you can run successfully)