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firhalfband
利用matlab提供的firhalfban函数设计阶数为16、通阻带容限为0.0001的半带滤波器。仿真测试滤波前后的信号时域图,回执滤波器的频率响应特性图(Provided firhalfban function using matlab design order of 16, through the 0.0001 stopband wool half-band filter. Simulation test filtered time domain signal before and after, receipt filter frequency response characteristic diagram)
- 2020-07-03 21:40:02下载
- 积分:1
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一个可用的很不错的DDS 频率合成程序,用VHDL语言编写
一个可用的很不错的DDS 频率合成程序,用VHDL语言编写-Available is a good DDS frequency synthesis procedures, using VHDL language
- 2022-11-29 23:55:03下载
- 积分:1
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UART串口传输的Verilog RTL
uart串口传输的verilog RTL级源码,已通过仿真验证。文件主要包含发送、接受位处理,发送、接受字节帧处理,对学习串口通信的朋友很有帮助-uart serial transmission verilog RTL-level source code has been verified by simulation. File mainly contains the send, receive digital processing, sending, receiving bytes of frame processing, serial communications, a friend of learning helps
- 2022-01-28 20:31:09下载
- 积分:1
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VHDL language used to achieve a display hours, minutes and seconds of the clock:...
用VHDL语言实现一个能显示时、分、秒的时钟:可分别进行时和分的手动校正;12小时、24小时计时制可选,12小时制时有上下午指示;当计时到预定时间(此时间可手动设置)时,扬声器发出闹铃信号,闹铃时间为10秒,可提前终止闹铃。-VHDL language used to achieve a display hours, minutes and seconds of the clock: when can be manually corrected and points 12 hours, optional 24-hour time system, 12-hour on the afternoon of instructions from time to time when the time to the scheduled time (This time can be manually set), the speaker sent alarm signals, alarm time was 10 seconds, the alarm can be terminated prematurely.
- 2022-04-27 22:51:31下载
- 积分:1
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Verilog版的C51核(OC8051)
Verilog版的C51核(OC8051)-Verilog version of the C51 core (OC8051)
- 2022-04-30 06:36:25下载
- 积分:1
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0001_EPM3064最小系统模块_带JTAG_LED_2mm插针
EMP3064的开发板板,原理图,verilog例子,板子说明,规格书,全套资料(EMP3064 development board, schematics, Verilog examples, board instructions, specifications, a full set of information)
- 2020-12-01 09:29:26下载
- 积分:1
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elevator
verilog语言写的一个四层电梯程序,有优先级的判断。(verilog language of a four-story elevator procedures to determine priority.)
- 2020-10-31 14:29:55下载
- 积分:1
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本实验教程选用Xilinx公司的产品X9572,与之配套的开发软件为ISE4.1i,可进行原理图的输入和VHDL硬件描述语言的输入,并且可利用Modelsim进
本实验教程选用Xilinx公司的产品X9572,与之配套的开发软件为ISE4.1i,可进行原理图的输入和VHDL硬件描述语言的输入,并且可利用Modelsim进行功能仿真和时序仿真。-In this study, selected Xilinx tutorial products X9572, with supporting the development of software for ISE4.1i, schematic can be input and VHDL hardware description language input, and can use Modelsim functional simulation and timing simulation.
- 2022-03-21 02:07:25下载
- 积分:1
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总结设计中的重点及注意的地方,常出现错误的地方等。
总结设计中的重点及注意的地方,常出现错误的地方等。-Summarize the design of the focus and attention of local, often the wrong place and so on.
- 2022-08-24 04:12:36下载
- 积分:1
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OFDM
OFDM完美出图,信噪比,16QAM星座图,加窗信号时域和频域波形图(Perfect figure, OFDM SNR, 16 qam constellation diagram, add window signal time domain and frequency domain waveform figure)
- 2021-04-15 15:08:54下载
- 积分:1