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pci144_vhdl
PCI vhdl for Fpga designer to design PCI IP
- 2007-12-23 20:58:15下载
- 积分:1
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实现一个简单的电子钟,时间(小时,分,秒)可以设置…
实现一个简单的电子钟,其时间(时,分,秒)可以设置和更改,设置和更改的同时不会影响其他显示的变化(相互独立)。-achieve a simple electronic bell, the time (hours, minutes and seconds) can set and change, Settings and change will not affect the other shows the change (independent).
- 2022-04-07 20:02:24下载
- 积分:1
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DAC1220
高精度直流信号源,DAC1220,20位分辨率,双极性输出(High-precision DC source, DAC1220,20 bit resolution, bipolar output)
- 2021-02-28 16:29:35下载
- 积分:1
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计数器的 vhdl 代码
我们使用此代码开发 plc 在 fpga 硬件计数器的程序
- 2023-02-08 13:05:03下载
- 积分:1
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9850sin_function
ad9850函数发生器 MSP430单片机驱动程序 扫频 DDS(AD9850 DDS)
- 2013-08-27 15:13:29下载
- 积分:1
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the-decoding-algorithm-of-ldpc
ldpc译码算法介绍及fpga verilog系统方案设计,包括log_bp算法、min_sum算法、scaling_min_sum算法等(introducing the ldpc code decoding algorithm and the related system design,including the log_bp,the min_sum and the scaling_min_sum)
- 2012-02-22 10:31:41下载
- 积分:1
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ADS8325caiyang konfgzhi
ADS8325caiyang konfgzhi
- 2023-04-14 05:15:03下载
- 积分:1
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16bit-multiplier
实现verilog16位乘法器,verilog新手(achieve 16-bit multiplier)
- 2021-04-01 21:09:08下载
- 积分:1
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8_1
一个具有置位、复位、左移和右移功能的八位移位寄存器/“01011010”序列检测器。移位寄存器电路端口为:异步清零输入端口rst,输入时钟clk,置数判断输入端口load,移位类型判断输入端口m,数据输入端口data[7:0],输出端口q[7:0]。序列检测器电路端口为:异步清零输入端口rst,输入时钟clk,串行数据输入端口d,输出标志端口s。(A eight bit shift register / 01011010 sequence detector with set, reset, left shift, and right shift function. Shift register circuit port is: Asynchronous Clear input port rst, input clock CLK, set the number to determine the input port load, shift type to determine the input port m, data input port data[7:0], output port q[7:0]. The sequence detector circuit port is: Asynchronous Clear input port rst, input clock CLK, serial data input port D, output flag port s.)
- 2020-12-17 08:29:12下载
- 积分:1
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vhdl programming from beginner level
vhdl programming from beginner level
- 2022-02-04 01:13:09下载
- 积分:1