存储示波器，功能齐全通过验证，毕业设计用

数码管显示程序，可以显示当前的数值，可以动态显示和静态显示 可以选择显示方式-Digital tube display program can display the current value, you can dynamically display and static displays can choose to display

Program to implement convolution through VHDL-Program to implement convolution through VHDL...

16QAM调制解调程序画出时域波形、 正交分量、同相分量波形，眼图，散点图等(16QAM modulation and demodulation process to draw time-domain waveform, quadrature components, in-phase component waveforms, eye diagrams, scatter plots, etc.)

该程序实现了一个FIR滤波加速器，该程序在FPGA板上开发，通过使用VHDL语言来定义RS232端口的使用(design a FIR Filter Accelerator based on FPGA board and RS232 interface using VHDL language. )

VHDL的初学者可以参考此VHDL加法器，相信会给你带来不小的收获-VHDL beginner can refer to the VHDL adder, I believe will bring you not a small harvest

ecc椭圆算法RTL,verilog源代码经过验证，用于FPGA或者ASIC(ECC elliptic curve encryption algorithm for Verilog implementation)

关于寄存器重命名register reallocation,VHDL-Register on rename register reallocation, VHDL

Verilog-RISC CPU

BCD码减法实现程序，非常完整，采用Verilog HDL语言实现。(BCD subtraction to achieve program code, very complete, using Verilog HDL language.)

时钟在单片机中的应用，用于控制中断及显示程序(Clock in the MCU application, used to control interrupt and display program)