存储示波器，功能齐全通过验证，毕业设计用

目前最新的OVL库，里面是标准的ASSERTION模块，支持VHDL刚Verilog，最近在做AXI协议验证的时候用到，分享下(The latest OVL(open verification library),including all standard module of assertions(VHDL and Verilog). It can be used into AXI Protocl Verification. Just share with you guys.)

说明：  是基于apb总线下的timer外设的rtl代码，主要包括apb_timer的master逻辑verilog，以及相应的开发文档，包括寄存器的描述，功能特性等。(RTL code is based on timer peripheral under APB bus, which mainly includes master logic Verilog of apb_timer and corresponding development documents, including the description of registers, functional characteristics and so on.)

反应速度测试小游戏，最小外设cpld游戏，带设计说明书(Reaction speed test games, the minimum peripheral cpld game, with design specifications)

TOPSWITCH-Ⅱ系列芯片在功率集成开关电源中应用的研究-TOPSWITCH-Ⅱ series of chips in the power switching power supply in the application of integrated research

ICA (Principal Component Analysis) algorithm and procedures, GSM is GMSK modulation signal generation, On neural network control.

超声波测距程序 适用传感器HC-SR04(The application of sensor HC-SR04 for ultrasonic range finder)

JOP内核字节码获取，很难找的东东，呕血之作-JOP core byte code access, it is difficult to find the price. Zhi for hematemesis

完成的是RS422信号的计数功能，并产生一定的触发信号-RS422 signals the completion of the count function, and produce a certain trigger signals

Quartus中实现的DDS 使用的是altera提供的IP core-DDS achieved Quartus using IP core provided by altera

这是一个计算机组成原理综合性实验：设计8位cpu。该cpu是8bit的代码，包含有4个寄存器，一个存储器，还有alu以及控制器。一共可以实现16条指令。(This is a computer composition principle of comprehensive experiment: Design 8 cpu. The cpu is 8bit code contains four registers, a memory, as well as alu and controllers. A total of 16 instructions can be achieved.)