m序列生成VHDL代码

基于USART的ARM与FPGA通信实验(Based on the ARM and FPGA communication experiment of USART )

Building the CPU datapath

说明：  数字下变频verilog实现，项目中常用模块(apply the digital down frequency in my project)

说明：  利用verilog写的PWM 程序，来实现产生呼吸灯的效果。(Using xerilog to generate breathing lamp)

usb读取，仅供参考，在实际应用中要更改以下数据。(Read usb data)

中频70M，30M带宽LFM信号，采样率为102.4M，，数字下变频后，还进行了三倍抽取，最后还得到I，Q两路信号 (IF 70M, 30M bandwidth LFM signal, the sampling rate 102.4M, under digital variable frequency after also carried out three times extracted, and finally also received the I and Q signals)

6264是一种8K×8的静态存储器.SRAM 的典型芯片有2KB 的6116、8KB 的6264 以及32KB的62256,其中6264 芯片应用最为广泛.(6264 is the 62256 typical chip SRAM.SRAM a 8K* 8 with 2KB 6116, 8KB 6264 and 32KB 6264 chip, which is most widely used. )

VHDL code of a counter Code VHDL d un compteur

VHDL Design of BCD to 7-segment decoder using PROM

pex8311代码实现 altera的fpga 代码编程 实现本地读写 pex8311_test