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业界标准的Verilog语法格式
verilog标准语法,还有很多的样例参考,学习的好资料。(Verilog standard grammar, there are many examples for reference, good learning materials.)
- 2020-06-15 22:50:02下载
- 积分:1
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USB 1.1 PHY的代码,verilog语言
USB 1.1 PHY的代码,verilog语言
USB 1.1 PHY的代码,verilog语言
USB 1.1 PHY的代码,verilog语言-USB 1.1 PHY code, verilog language USB 1.1 PHY code, verilog language
- 2022-01-25 23:39:51下载
- 积分:1
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"digital circuit EDA portal
《数字电路EDA入门-VHDL程序实例》---交通灯程序例子-"digital circuit EDA portal-VHDL program examples"-- traffic lights procedures example
- 2022-02-19 21:55:09下载
- 积分:1
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扰码器的verilog实现,参考802.11a相关标准
扰码器的verilog实现,参考802.11a相关标准-Scrambler in verilog implementation
- 2022-03-13 09:09:35下载
- 积分:1
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sm4_Verilog
sm4 VERILOG 代码实现及其在无线网络3G中的应用(sm4 VERILOG)
- 2020-08-11 20:58:27下载
- 积分:1
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Complete-RAM
ram 64KB designed by haneesh in verilog
- 2011-07-15 00:57:01下载
- 积分:1
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shuzizhong3
数字钟VHDL软件设计,包含多种功能,报时,12,24切换,调时(The design of VHDL digital clock software, including a variety of functions, timer, 12,24 switch, adjustable)
- 2016-05-27 11:41:22下载
- 积分:1
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Verilog 下 16位除法算法程序,高精度,固定17个时钟周期
Verilog 下 16位除法算法程序,高精度,固定17个时钟周期-Verilog under 16 division algorithm procedures, high-precision, fixed in 17 clock cycles
- 2022-01-27 13:18:06下载
- 积分:1
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crc循环冗余校验码,用于对传输信号进行编码校验,是信息更可靠...
crc循环冗余校验码,用于对传输信号进行编码校验,是信息更可靠-crc cyclic redundancy check code used to transmit coded signals to verify, the information is more reliable
- 2022-12-26 06:05:03下载
- 积分:1
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Dice_game
VHDL Project for beginners. Electronic dice game. Perfect for Spartan devices.
- 2011-02-22 22:07:59下载
- 积分:1