这是一个用vHDL语言实现的移位器，可以实现移位功能

低通滤波器在QUARTUS7.0开发环境下的文本与框图结合的实现方法的源代码-Low-pass filter QUARTUS7.0 development environment in the text and diagram combination of methods to achieve source code

EP1C6_EP1C12核心板原理图，方便自己动手做板学习FPGA-EP1C6_EP1C12 core board schematics, do-it-yourself to do to facilitate learning FPGA board

数字秒表的VHDL设计,能精确到百分秒,在6位数码管上显示,分别有秒,分,小时,通过目标芯片EPF10KLC84-4验证-VHDL design of digital stopwatch, accurate to the percentage of seconds in the six digital tube display, respectively, have seconds, minutes, hours, through the target chips EPF10KLC84-4 verification

FPGA控制AG9226进行采样的代码,并用signaltap测试了一下其正确性

四阶数字滤波器 用不同的算法设计数字滤波器，并且有详细的是用方法(Fourth-order digital filter design with a different digital filter algorithms and a detailed method is)

quartus工具入门文档，altera公司官方软件翻译全文。-tool for quartus entry documents, altera company official translation of the full text of the software.

FPGA测序和DDS产生各种波形程序，用Atral器件开发(FPGA sequencing and DDS generate various waveform programs.)

Hexadecimal to 7 segments

Material to learn how to use system verilog and how to write testbenches for verification.

LTE is an abbreviation for Long Term Evolution.