EP1C6_EP1C12核心板原理图，方便自己动手做板学习FPGA

saber的仿真模型，是一个电源的，经过调试已经成功(The simulation model of the saber, is a power, after commissioning has been successfully)

many matlab code with Fftseq ,uniform to gauss AM DSB FM modulation

altera嵌入式设计大赛文章，车载cots设计实现-Embedded Design Contest altera article, cots Car Design

这是一款CPLD的在线调试软件。能够满足用于学习者的一般要求。-This is a debugging software online CPLD. Be able to meet the general requirements for learners.

使用vhdl实现的1024点的FFT算法-Using vhdl implementation of the 1024-point FFT algorithm

一个任意整数分频程序,采用VHDL语言编写，编译通过-An arbitrary integer frequency procedure for the VHDL language, the compiler through

一个交通灯的vhdl语言实现 用 ＶＣ的　　１．在指定的文件夹内查找某个文件 　　　　　２．获取系统文件夹的路径， 要求显示windows system temp 当前目录的路径 Ｃ语言　　跳马问题：在５＊５的棋盘上，以编号为１的点出发，按日只跳马，要求不重复地跳所有位置，求出符合规则所有跳马的方案 　　　　１　　６　　１５　　１０　　２１ 　　　　１４　９　　２０　　５　　　１６ 　　　　１９　２　　７　　　２２　　１１ 　　　　８　　１３　２４　　１７　　４ 　　　　２５　１８　３　　　１２　　２３ -a traffic light VHDL language of a VC. The designated folders to search within a document 2. Access to the system folder path, requested that the current windows system temp directory path C language vault : 5* 5 in the chessboard to the No. 1 starting point, the only daily vault and asked not to repeat all locations to jump to get in line with all rules of the program vault 1 6 15 10 21 14 9 20 5 16 19 2 7 22 11 8 13 24 17 4 25 18 3 12 23

SPI串行总线接口的Verilog实现，详细讲解实现过程。-SPI serial bus interface Verilog realization elaborate on the realization of the process.

基于vhdl的PWM发生器-VHDL-based PWM generator

说明：  假设每个从设备中有可访问APB寄存器16个，位宽均为32比特，16个寄存器的访问地址计算方式为 基址 +　寄存器编号左移２位（byte 偏移）(Assuming that there are 16 accessible APB registers in each slave device, the bit width is 32 bits, and the access address of 16 registers is calculated by base address + register number left shift 2 bits (byte offset).)