AES 128 Crypto Core

说明：  在quartus下搭建的数字锁相环，能实现频率自动跟踪。(The digital phase-locked loop built under quartus can realize automatic frequency tracking.)

Fun little FPGA that plays a portion of Habanera

VHDL学习总结，简要概括了VHDL，非常适合做学习的总结-VHDL study conclusion, a brief summary of VHDL, very suitable for learning to do a summary of

LED闪烁的VHDL代码

基于fpga的位同步信号提取仿真 使用vhdl语言 quartus(To use vhdl language quartus fpga bit synchronization signal extraction-based simulation)

Xilinx,Altera,ARM,AVR,S52,Lattice等系列FPGA的下载线电路图和PCB(Xilinx, Altera, ARM, AVR, S52, Lattice series FPGA download cable circuit diagram and PCB)

papers based on distributed arithmetic.

硬件描述语言,verilog HDL,实现了解码器的设计-hardware description language, verilog HDL, the decoding of Design

In this case is a QPSK algorithm code for mapping the interleaved code, using VHDL language. This code provide the method of mapping the code by using QPSK algorithm.

由于衍射、散射、反射和稀疏等环境损伤的增加，其后果是信号视线的丧失和干扰。自适应信号处理可以克服这些缺陷。该代码是用甚高速硬件描述语言（VHDL）编写的，用以滤除高频，减少噪声和干扰。