ModelSim Quick Start Guide, incidental text in an example of source code.

DDS波形生成器verilog语言书写（FPGA型号cy4以上）(DDS generate verilog)

Conduct a digital system ( electronic lock ) using hierarchic methodology . An electronic lock is a device that allows access or opening of a system , as long as the key or combination to enter match with which it is predefined in said lock .

用vhdl实现脉冲宽度可控的一简单程序 仿真环境MAXPLUS-(use VHDL to achieve controllable pulse width of a simple process simulation environment Segments-)

数字频率计的设计，显示0~999的频率 整个程序代码都是通过vhdl语言来完善的 功能模块多样，详细的介绍了多模块的各个功能

vga显示彩色图像ip，alter开发板-vga display color image,vhdl,quartus

利用FPGA内核产生SPWM波，并且频率可调(The FPGA kernel is used to generate SPWM waves, and the frequency is adjustable)

基于DVI协议动态全彩LED大屏幕发送卡设计与实现,成本比较低,效果很好,可以实现高清视频(Dynamic full-color LED large screen based on the DVI protocol send a card design and relatively low cost, good effect, and can achieve high-definition video)

浮点数 矩阵乘法模块 verilog语言编写 可直接调用(Floating-point matrix multiplication module can directly call verilog language)

用VHDL和verilog实现的四人抢答器-using VHDL and verilog realization of four Responder

说明：  计算机组成原理实验多时钟周期CPU设计，包含VHDL代码的设计，实验电路图，实验详细截图。(Computer component experiments designed more CPU clock cycles, including VHDL code design, test circuit, test detailed screenshots.)