ModelSim Quick Start Guide, incidental text in an example of source code.

VHDL语言写的频率计的程序，内带完整的技术报告-VHDL write the frequency of procedures, brought integrity of the technical report

32位存储器Verilog附带test文件，可以在modulesim仿真 还有加法、减法器，译码器等常用Verilog器件，都附带仿真test。(Memory test with Verilog)

实现beep发出1234567的音乐声音-beep 123456

可编程器件厂商Altera出品的8b10b编码器源代码(Giga8b10b v10)

vhdl 中各种数据类型的转换实现,可以调用函数库实现-date type change

Verilog HDL 读取EEPROM项目的详细构建(Verilog HDL EEPROM read the detailed construction)

实现矩阵相乘，即点积运算，为VERILOG语言。可以根据自己的需要改变维数，采用了流水线的结构(Achieve matrix multiplication, ie dot product operations, for VERILOG language. You can change the dimension according to their needs, using a pipeline structure)

FPGA与DAC芯片的SPI接口驱动，实现串行数据的传输。(Realizing the communication between FPGA and DA chip)

完整的PIC16系列单片机verilog描述-A complete description of PIC16 series of microcontrollers verilog

以太网协议 TCP/IP/DHCP协议verilog实现(Ethernet IP/TCP/DHCP verilog source code)