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DDS波形发生器
DDS波形生成器verilog语言书写(FPGA型号cy4以上)(DDS generate verilog)
- 2017-07-17 22:25:11下载
- 积分:1
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Cerradura
Conduct a digital system ( electronic lock ) using
hierarchic methodology .
An electronic lock is a device that allows access or
opening of a system , as long as the key or combination to enter match
with which it is predefined in said lock .
- 2014-10-10 15:41:14下载
- 积分:1
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pulse_change
用vhdl实现脉冲宽度可控的一简单程序 仿真环境MAXPLUS-(use VHDL to achieve controllable pulse width of a simple process simulation environment Segments-)
- 2005-07-24 11:53:57下载
- 积分:1
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基于fpga数字频率计的设计
数字频率计的设计,显示0~999的频率
整个程序代码都是通过vhdl语言来完善的
功能模块多样,详细的介绍了多模块的各个功能
- 2022-03-13 10:54:30下载
- 积分:1
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VGA显示彩色图像,VHDL,Quartus
vga显示彩色图像ip,alter开发板-vga display color image,vhdl,quartus
- 2022-09-20 17:40:02下载
- 积分:1
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SPWM
利用FPGA内核产生SPWM波,并且频率可调(The FPGA kernel is used to generate SPWM waves, and the frequency is adjustable)
- 2020-12-08 20:19:19下载
- 积分:1
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DVI_LED
基于DVI协议动态全彩LED大屏幕发送卡设计与实现,成本比较低,效果很好,可以实现高清视频(Dynamic full-color LED large screen based on the DVI protocol send a card design and relatively low cost, good effect, and can achieve high-definition video)
- 2012-08-03 13:08:44下载
- 积分:1
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altfp_matrix_mult
浮点数 矩阵乘法模块 verilog语言编写 可直接调用(Floating-point matrix multiplication module can directly call verilog language)
- 2013-12-18 15:08:36下载
- 积分:1
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用VHDL和verilog实现的四人抢答器
用VHDL和verilog实现的四人抢答器-using VHDL and verilog realization of four Responder
- 2023-07-17 00:15:04下载
- 积分:1
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CPUdesign
说明: 计算机组成原理实验多时钟周期CPU设计,包含VHDL代码的设计,实验电路图,实验详细截图。(Computer component experiments designed more CPU clock cycles, including VHDL code design, test circuit, test detailed screenshots.)
- 2020-09-07 19:28:05下载
- 积分:1