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Verilog code to calculate Sobel
Verilog code to calculate Sobel
- 2022-03-24 08:25:30下载
- 积分:1
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这里面有许多vhdl的例子,相信对这语言的初学者受益匪浅
这里面有许多vhdl的例子,相信对这语言的初学者受益匪浅-There are many examples of vhdl, I believe that beginners benefit from this language
- 2023-06-28 10:40:04下载
- 积分:1
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DCM_SP
数字时钟管理器,xilinx公司开发板集成时钟,实现分频、倍频等功能。(Digital clock managers, xilinx development board integrated clock divider, multiplier, and other functions.)
- 2021-02-19 09:59:44下载
- 积分:1
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freeDev数字应用开发板中的VGA控制器的IP核的verilog实现
freeDev数字应用开发板中的VGA控制器的IP核的verilog实现-freeDev digital application development board of the VGA controller IP core implementation of the verilog
- 2022-03-01 11:34:28下载
- 积分:1
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This is a realization of I2C interface VHDL module, I2C protocol to achieve
这是一个I2C接口的VHDL实现模块,实现I2C协议-This is a realization of I2C interface VHDL module, I2C protocol to achieve
- 2023-08-26 08:25:03下载
- 积分:1
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CCDDRIVE(TCD1206UD)
关于一款线阵CCD TCD1206UD 的驱动设计,波形符合工作要求(On how the system in SOPC using HDL language development from a custom IP core)
- 2020-11-14 09:19:42下载
- 积分:1
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HDLC协议
HDLC协议的FPGA实现,运用了VHDL语言,主要就是解封帧HDCL,平切添加了外部接口
- 2022-07-15 03:35:09下载
- 积分:1
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counter4b
Vivado同步计数器VHDL设计 具有异步复位和同步预置数功能 同步计数器同步计数器同步计数器(The Vivado synchronous counter VHDL is designed with asynchronous reset and synchronous preset function, synchronous counter, synchronous counter and synchronous counter.)
- 2021-03-26 14:29:13下载
- 积分:1
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DA_Test
说明: 基于CycloneV FPGA与电阻网络的数模转换器代码,能够实现键控更改频率,通过ROM IP核存储波形数据。(Digital to analog converter code based on cyclonev FPGA and resistance network can realize keying change frequency and store waveform data through ROM IP core.)
- 2020-03-29 22:36:29下载
- 积分:1
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spartanII 是xilinx公司提供的一款高性能FGPA芯片,本文详细介绍spartanII的体系结构和编程!...
spartanII 是xilinx公司提供的一款高性能FGPA芯片,本文详细介绍spartanII的体系结构和编程!-spartanII Xilinx is provided by a high-performance chip FGPA, spartanII This paper describes the architecture and programming!
- 2022-03-03 02:06:35下载
- 积分:1