基于VHDL语言描述的一个分频器，根据端口值，可作为四分频，八分频等分频器使用。...

本文件介绍的是用VerilogHDL语言设计分频器和32位计数器.(This paper presents the design using Verilog HDL language Frequency Divider and 32 counters.)

altera fpga ep3c25器件微处理器开发，niosii+sram, 已编译通过，可直接下载到开发板(altera fpga ep3c25 the development of microprocessor devices, niosii+ sram, compiled through, can be directly downloaded to the development board)

说明：  用verilog编辑的中值滤波器！语言旁表有注释方便理解！(Using Verilog editor median filter! Language beside the table annotated to facilitate understanding!)

标准RS422 Verilog源代码， 传输波特率可以修改， FPGA上可以工作(Standard RS422 verilog communication source code, buardrate can be updated and it is fully work in FPGA )

it has 6 packages of 8051 sources,including source code(VHDL and Verilog),dc scripts, pdfs, netlists etc. and a MIPS IP package

该程序实现的N位全减器，首先实现一位的减法器，之后实现N位全减器。-Program of the N-bit-wide reduction, the first realization of a subtraction for, after all N-reduction devices.

说明：  这是一个关于dQPSK的Matlab程序 这是一个关于dQPSK的Matlab程序 (This is a dQPSK the Matlab program This is a dQPSK the Matlab program)

this a LCD Driver VHDL code -this is a LCD Driver VHDL code

FPGA与DSP的EMIF通信，EMIF的RAM这方面相应的程序(FPGA and DSP EMIF communication)

这个是专门用在ALtera第二代PLD MAXII上的16位微处理器IP核，文档齐全-this is the ALtera devoted second-generation PLD MAXII on the 16-bit microprocessor IP core, complete documentation