该程序实现的N位全减器，首先实现一位的减法器，之后实现N位全减器。...

三相PWM整流，实现功率双向流动,可保持直流侧电压稳定(three-phase PWM rectifier, power can bidirectional flow ，can maintain the stable DC voltage)

说明：  模拟交通灯 verilog CPLD EPM1270 源代码(Simulation of traffic lights verilog CPLDEPM1270 source code)

Multiplication in Verilog code

EDA/VHDL数字频率计，可编程逻辑门阵列，EDA课程设计(EDA/VHDL digital frequency meter, programmable logic gate array, EDA curriculum design)

我用FPGA来实现，这是一个出租车计价器，用来计算里程，我已在Quartus 2实现。(I used the FPGA to achieve, this is a taxi meter, calculate the mileage, I have been in quartus 2 to achieve.)

Opencore的IP Core，有实际合成过，可以用，大家参考-Opencore of the IP Core, there is a practical synthesis that we could use, we refer to see

该模块已经成功运用在xilinx xc6slx45t，xc6slx75t多个产品中，经过实践证明，采用dna及其加密算法加密是一种成本低廉（无需另外加密芯片）可靠的加密手段。Xilinx Spartan-6 FPGA读取DNA数据并进行比较，产生比较结果信号输出。附带有xilinx DNA.ppt说明及调试注意事项。(The module has been successfully used in xilinx xc6slx45t, multiple xc6slx75t products, proven, and the encryption algorithm uses dna is a low-cost (no additional encryption chip) reliable means of encryption. Xilinx Spartan-6 FPGA reads the data and compare DNA to produce a comparison result signal output. Xilinx DNA.ppt comes with instructions and commissioning notes.)

SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals in various formats. The cores connect using AXI-streams. Most configurations (resolution, framerate, colordepth, etc.) are set at compile-time using Verilog parameters. See svo_defines.vh for details on those parameters.

这通过反馈来实现一个 17 位伪随机的无符号计数器异或的位 0 和 3。 注意 ︰ 如果也绝不是独家使用相反，这会反相平行的位模式 & 这将意味着所有位都零是一种有效模式和所有那些不都是有效。  目前所有的都是有效的。

Verilog写的 8 位超前进位加法器-Verilog write 8-bit CLA