这个是专门用在ALtera第二代PLD MAXII上的16位微处理器IP核，文档齐全...

VHDL的四选一选择器-VHDL four elected a selector

RISC-V 芯片设计规范,很有参考价值，开源芯片设计必备参考资料，希望对大家有帮助。(The RISC-V Foundation is chartered to standardize and promote the open RISC-V instruction set architecture)

60进制减法 相比较 代码效率高 可以进行级联-60 compared to 229 subtraction efficient code can be concatenated

A/D采集的数据缓存进入fifo，并通过读信号将FIFO中的数据送入网口(A/D sample data buffer to fifo,and then read enable to ethernet.)

this is the vhdl code for the arithmetic logic unit.enjoy!

该程序实现最小频移键控信号的调制解调，经测试无误。(The program implements minimum shift keying signal modulation and demodulation, tested and correct.)

一个小程序,弹跳消除电路,可消除按健的毛刺干扰-a small procedure, bouncing elimination circuit, according to remove the burr-interference

本章介绍了两个EDA技术的综合应用设计实例:数字闹钟和直接数字频率合成器DDS。-EDA chapter describes the two technologies integrated application design example: digital alarm clock and direct digital synthesizer DDS.

8051IP 核源代码-8051IP nuclear source code

Interface for ADS8361 TI ADC IP Core for ALTERA NIOS2