这个是专门用在ALtera第二代PLD MAXII上的16位微处理器IP核，文档齐全...

数字时中（VHDL）-Numbers in (VHDL)! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !

扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现-Frequency-hopping communication QUARTUS7.0 expanded development environment in the VHDL source code and the achievement of the overall block diagram

用vhdl设计实现的多功能电子钟，可有日历，闹钟，修改等多种功能-With VHDL Design and Implementation of the multi-functional electronic bell, can have a calendar, alarm clock, to amend a variety of functions such as

卷积程序的Verilog程序，实现卷积功能(Convolution program Verilog program to achieve convolution function)

模块化分散聚集 DMA 是连续或非连续的转移。如正常 DMA 或散点图聚集 DMA 配置的输入或输出的部分。

VHDL 波形防止抖动程序,学习试验材料(VHDL prevent jitter waveform procedures, the pilot study materials)

VHDL语言实现PWM信号，非常方便的使用-VHDL language realize PWM signal, very convenient to use

文件描述的是SDH 指针处理和系统同步代码 veriolg(SDH pointer processing and system synchronization code veriolg of file Description)

工程实用观点，简单介绍集成电路的传统设计语言现状。(Practical engineering point of view, the traditional integrated circuit design brief language status.)

本程序实现两个整数平方和相加并且输出结果-the program two integers and the sum of squared output