这是一个LCD驱动的VHDL代码

本书作者为夏宇文，详细讲解了从算法设计与验证到硬件逻辑实现的过程，要求读者有一定的verilog基础(This book author XIA Yu-Wen gave a detailed account from algorithms to hardware logic design and verification of implementation process, requiring readers to have some basis for verilog)

说明：  1、能正确显示输入信号频率； 2、测量频率范围为1Hz ~ 999999Hz； 3、测量结果以十进制数字显示； 4、能测量幅值较小的信号频率； 5、有自动刷新输出数据的功能（如5s刷新一次）； 6、有自检模块（如产生100Hz的校准方波）；(1. It can correctly display the input signal frequency; 2. The frequency range of measurement is 1Hz ~ 99999hz; 3. The measurement results are displayed in decimal; 4. It can measure signal frequency with small amplitude; 5. It has the function of automatically refreshing the output data (e.g. once in 5S); 6. Self checking module (such as generating 100Hz calibration square wave);)

一个简单的键盘接口模块程序，对键盘输入的数据和时钟信号进行过滤。过滤后的数据信号PS2Df将被送入两个11位移位寄存器中(A simple keyboard interface module program filters keyboard input data and clock signals. The filtered data signal PS2Df will be fed into two 11-bit displacement registers.)

开发环境：maxplus2 a/d convortor-development environment : maxplus2 a/d convortor

一个关于跨越异步时钟边界传输数据的解决方案(The solution of transfering data across asynchronous clock boundary.)

这是用verilogHDL写的m序列发生器，简单易用，代码非常易读(It is written verilogHDL m sequence generator, easy to use, the code is very easy to read)

vhdl语言实现的频率发生器，可以产生不同的频率-A frequency generator wirriten by VHDL, which can generate different frequecies.

vhdl的3-8译码器-instantiate the 3-8 decoder

利用AT89C51实现LCD日历电子钟源码-AT89C51 realization of the use of electronic LCD calendar clock source

fpga串口的接收程序基于verilog语言拿走不用谢。(The receiving program of FPGA serial port is based on Verilog language.)