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ANC_LMS
verilog描述的基于LMS的自适应噪声消除器ANC算法。用于数字音频处理。(The verilog Description LMS-based adaptive noise canceller ANC algorithm. For digital audio processing.)
- 2012-10-29 21:43:33下载
- 积分:1
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LCD1602-TEST
利用verilog驱动LCD1602
本实验是用LCD1602显示英文。(LCD带字库)(//Use verilog driver LCD1602// video tutorial for all of us 21EDA e-learning board// The experiment is LCD1602 display in English. (LCD with font))
- 2013-12-16 13:51:35下载
- 积分:1
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14_SDRAM
高速流水的SDRAM控制器,最高速度可达速度在200M左右(high speed SDRAM controller)
- 2019-06-17 18:43:54下载
- 积分:1
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使用VHDL代码的FIR滤波器的设计
fir filter design using vhdl codes
- 2022-02-26 18:55:51下载
- 积分:1
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pdf
说明: 一种基于FPGA的调频连续波方位向多通道
FMCW SAR的实时成像信号处理方法及FPGA,包
括:步骤一、计算重构矩阵;步骤二、重构方位向
多通道数据,包括:步骤2 .1、对各个通道的回波
数据沿方位向分别间隔补零,并进行方位向傅里
叶变换;步骤2 .2、将方位向傅里叶变换之后各个
通道方位向相同位置的点组合为一个向量并与
重构矩阵相乘,得到重构完成的方位向数据;(An azimuth multichannel FMCW based on FPGA
FMCW SAR real-time imaging signal processing method and FPGA, package
Including: Step 1: calculate the reconstruction matrix; step 2: reconstruct the orientation
Multichannel data, including: step 2.1, echo of each channel
The data is compensated with zero along the azimuth direction respectively, and the azimuth Fourier is carried out
Step 2.2, after the azimuth Fourier transform
The points of the same position in the channel azimuth are combined into a vector and are connected withThe reconstruction matrix is multiplied to get the reconstructed azimuth data
Step 2.3. Repeat step 2.3 for the data of different distance gates)
- 2020-02-07 19:47:41下载
- 积分:1
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MUX
Multipleksor
3 to 1 - 3x1bit in, 1x1bit out
- 2013-09-18 16:21:25下载
- 积分:1
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file_read vhdl code provide by my teacher for reading file into FSM
file_read vhdl code provide by my teacher for reading file into FSM-file_read vhdl code
- 2022-03-12 05:55:24下载
- 积分:1
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cpu-maxplus
MaxplusII编写的简易cpu,可实现简单加减法等操作(MaxplusII summary prepared by the cpu can realize simple addition and subtraction, etc)
- 2007-06-08 17:55:10下载
- 积分:1
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布斯算法结构的 VHDL 代码
布斯算法用于在计算机体系结构的两个二进制现在的乘法。随着处理器为转移的运行情况良好,不能轻易做乘法这就是为什么正在使用它。
- 2022-08-08 00:31:29下载
- 积分:1
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Verilog_HDL源码, Verilog_HDL源码
Verilog_HDL源码, Verilog_HDL源码-Verilog_HDL source, Verilog_HDL FO
- 2022-06-21 00:23:39下载
- 积分:1