VGA显示驱动程序编写的Verilog HDL

用verilog语言编写的串口读写程序，波特率可调，亲测可用。(this is a program for UART by verilog, which is useful.)

Shift reg in vhdl, a first example to start

异步的fifo,写时钟和读时钟相互独立，能够对数据进行缓存处理。希望对大家有用(Asynchronous fifo, write clock and the read clock independent of each other, capable of processing the data cache. I hope useful)

PS2 Module for Altera DE2

这是个关于verilog入门的文档，有同志对verilog感兴趣，可以下载此文档，以供参考。(This is a verilog entry on the document, there are comrades of the verilog interested, you can download this document for reference.)

说明：  一个编码解码系统，其中包含一个信号发生器（用查找表方式实现）、一个m序列生成器（用来编码和解码用）、一个FiFo队列用来做缓存以及用串口方式进行收发读取数据。(An encoding and decoding system, which includes a signal generator (implemented by look-up table), an m-sequence generator (used for encoding and decoding), a FIFO queue for caching, and a serial port for receiving, transmitting and reading data.)

工程实用观点，简单介绍集成电路的传统设计语言现状。(Practical engineering point of view, the traditional integrated circuit design brief language status.)

tdma参数化模块。可以自动生成2的n次的tdma哥时隙，用户可根据需要自己配置参数(tdma see the number of model lumps. 2 n basis following manner tdma chance possible 以自 dynamic generation, for root needed self-placement see number)

AMBA总线规范，能对从事嵌入式的同行们有一些帮助，让大家更好的理解ARM 结构和AMBA 体系(AMBA Specification)

basic verilog code on siso, piso, sipo