VGA显示驱动程序编写的Verilog HDL

基于FPGA的等精度频率计，包括工程，doc和一些查找资料(An equal precision frequency meter based on FPGA, including engineering, Doc, and some lookup data)

Verilog module containing a synthesizable CRC function // * polynomial: (0 1 8) // * data width: 8-Verilog module containing a synthesizable CRC function //* polynomial: (0 1 8) //* data width: 8

FFT implementation using C program

一个游戏程序vhdl源码，供大家参考，希望有兴趣的人下载-VHDL source code of a game program for your information, I hope those who are interested in downloading

vmm log 验证平台，采用vmm搭建 (vmm log verification platform, built by vmm)

Counter written in VHDL.

DESCRIPTION OF FULL ADDER

说明：  利用vhdl语言编写的译码器程序，采用两种不同方式(The use of language decoder vhdl program, using two different ways)

串口通信例程，使用FIFO数据缓存。Verilog源码，基于FPGA的uart开发，加深理解。(uart communication)

结合XILINXCPLD所做的模拟RS232通信verilog源程序-XILINXCPLD combine the simulation RS232 communication Verilog source