VGA显示驱动程序编写的Verilog HDL

Bone microphnoe simulator. this is a trial to de-noise the bone microphone signals. This also utilizes om-lsa algorithm

Blessing_3_v3_9_6稳定盈利set，仅限AUDNZD货币对，周期M1。 使用本压缩包内的SET，LAF默认是15，根据历史测试来看具有较大的风险，需要手动规避数据。 合理设置为LAF=8，请自行设置和调试，找到自己合适的风险值。 (Blessing_3_v3_9_6 stable profit set, only AUDNZD currency pairs, cycle M1. Use this package in the SET, the default is 15 fans, according to the angles of history test has great risk, need to avoid data manually. Reasonable set to fans = 8, please make your own setting and debugging, find their proper risk value.)

基于fpga的uart串口通信协议，64位数据(Uart communication protocol based on fpga, 64-bit data)

用vhdl语言编写的程序，可以播放乐曲，有分频模块，可播放梁祝等歌曲。

用vhdl实现24小时计数器，方法简单实用。 仿真环境MAXPLUS--use VHDL to achieve 24-hour counter, simple and practical method. Simulation environment Segments-

图像采集 VGA输出 图像的边缘 ov7670(V image acquisition VGA output image edge)

卷积码(2,1,7)编码器，一个输入，两个输出(Convolution code (2,1,7) encoder, an input and two outputs)

verilog HDL编写的浮点除法器，编译通过，可综合。压缩包包含三个文件。(verilog HDL write floating-point divider, compile, can be integrated. Archive contains three files.)

cpld/fpga RS(204,188)译码器的verilog程序-cpld/fpga RS (204,188) decoder of the Verilog program

ＲＳ编码在ＦＰＧＡ上实现的理论和方法，对设计ＲＳ编码很有帮助，且ＦＯＧＡ资源占有少-RS coding in the FPGA to achieve the theory and method useful for design RS encoding, and possession of less FOGA resources