VHDL语言教材

this code for integrator for 8 bit signal

VGA interface using Spartan3E board from DIGILENT.Labview .vi

并口通讯代码 并口通讯代码（调试通过） --该代码目前能实现单个字节的收发-Parallel communications code (debugging through)-- The code can now achieve a single byte of Transceivers

FPGA to design in ECU, very help for engineer

设计一个十进制计数器模块，输入端口包括 reset、up_enable 和 clk，输出端口为 count 和 bcd，当 reset 有效时（低电平），bcd 和 count 输出清零，当 up_enable 有效时（高电 平），计数模块开始计数（clk 脉冲数），bcd 为计数输出，当计数为 9 时，count 输出一 个脉冲（一个 clk周期的高电平，时间上与“bcd=9”时对齐）(Design of a decimal counter module, input port, including the reset up_enable clk, output port for the count and bcd, when reset is active (low), the bcd and count output cleared up_enable active (high), count module starts counting the (the CLK pulse number), the BCD count output when the count 9, the count output of the high level, the time of a pulse (a clk cycle with " bcd = 9" when aligned))

用于sopc builder添加组件用的ps/2 键盘 ipcore-Sopc builder used to add components used ps/2 keyboard IPCore

VHDL源码 VHDL源码 -VHDL source VHDL source VHDL source

inter integrated circuit i2c protocol

fsk调制与解调，此程序经过验证，可以运用，通讯方面的同学可以用-FSK modulation and demodulation, this procedure has been verified and can use communications students can use

说明：  千年服务端修改工具，千年db数据在线修改(Millennium server modification tool Millennium server modification tool)