PCI IP核vhdl源码，Xilinx原版

异步FIFO 输入: 16bit 输出:16bit 深度:256(Asynchronous FIFO Input: 16bit Output: 16bit Depth: 256)

802.11a Transmitter implementation Using Verilog

可直接用于zedboard上的串口通信，利用zynq7000的pl部分实现一个简单的UART串口通信(Can be used directly on the zedboard serial communication, the use of zynq7000 PL part of the realization of a simple UART serial communication)

说明：  基于FPGA设计的串口发送及接收程序，波特率可调(FPGA - based serial port sending and receiving)

是基于FPGA的5620的数模转换芯片底层的应用程序，希望有用。(Is a digital-analog converter chip underlying the 5620 FPGA-based applications, and I hope useful.)

新版 小米抢购器 -源码 已经测试，代码很有用，已经抢了好几个小米3了，希望对大家有用(The new millet to snap up- source Have test, the code is useful, has robbed several millet 3, hope useful for everyone)

输入正确密码显示绿灯亮 错误时红灯亮并发出警报 运行环境为matplaux 2-a afdg jhg dfgh r fbnrfer

matlab file for image contrast..

一个电子中的verilog实验源代码。适合verilog初学者学习参考-an electronic experiments of Verilog source code. Suitable for beginners learning Verilog reference

说明：  HDB3编码通过verilog实现，通过modelsim仿真(HDB3 coding is implemented by Verilog and simulated by Modelsim)