乘法器,实现了乘法和除法的功能,能够进行32位的运算

说明：  FPGA的fifo与dsp的emif接口测试程序(EMIF interface test program for FIFO and DSP of FPGA)

说明：  vivado lwip 应用文档 基于zynq 7020(vivado lwip example text of zynq)

maxplus2为开发环境 vhdl编写的 扫描 程序-maxplus2 VHDL development environment for the preparation of a scanning program

基于Verilog HDL的完整数字跑表工程，在试验机台上运行验证通过了的。 用8位7段数码管分别显示微妙，秒，分。 有开始，暂停，复位功能。 学习VerilogHDL的经典例子，添加了显示功能。-Complete Verilog HDL-based digital stopwatch works in the test machine is running verify pass the platform. With 8-bit 7-segment digital tube showed the delicate, seconds, minutes. Has started, pause, reset. Learning VerilogHDL classic example of adding a display.

turbo码的编码程序,verilog HDL,在ISE环境中(turbo code encoding process)

说明：  基于VHDL出租车的设计，实现开动、停止的收费功能。(VHDL-based cab design, implementation and running, stop the charging function.)

高速FIFO，verilog设计。速度高达130Mhz(High-speed FIFO, verilog design. Speed up to 130MHz)

这是基于Quartus2 开发环境和verilog hdl语言写的38译码器(This is based development environment and Quartus2 verilog hdl language used to write decoder 38)

空调温控电路有限状态自动机， 有ＴＥＭＰ＿ＨＩＧＨ和ＴＥＭＰ＿ＬＯＷ 分别与传感器相连用语检测室内温度．-air-conditioning temperature control circuit finite state automaton, and TEMP_LOW TEMP_HIGH with sensors connected to the indoor temperature detection terminology.

fpga code for pong game