乘法器,实现了乘法和除法的功能,能够进行32位的运算

说明：  “基于 ROM 的 LCD图片显示实验 ”中利用 FPGA 片上存储资源存储图片，并通过 LCD接口将图片显示到 LCD屏幕上。但是由于 FPGA 片上存储资源有限，只能存储分辨率较小的图片(In the experiment of LCD image display based on ROM, FPGA on-chip storage resources are used to store pictures, and the pictures are displayed on LCD screen through LCD interface. However, due to the limited on-chip memory resources of FPGA, it can only store images with smaller resolution)

使用verilog写的32位浮点数加法模块、浮点数乘法模块、浮点数除法模块、浮点数指数模块。指数模块是综合前面三个例化成泰勒级数求指数，迭代次数（可设置）决定了精度。(Use verilog write 32-bit floating-point addition module, floating-point multiplication module, floating-point division module, the floating point number index module.Index module is a comprehensive index of the front three cases into Taylor series for calculating index, the number of iterations can be set to determine the precision)

本项目接收高清 sdi 广播的视频，并将其转换为 HDMI 接口的显示器上显示。 这个项目只需要 20 位的视频数据和从它和使用标志首先 YCbCr 视频数据转换为 RGB 数据，然后编码到 HDMI 提取时间标志。 本模块需要 74.25 MHz 的时钟。

基于单片机的DDS数字信号发生器设计，可以产生正弦波。三角波等(Design of DDS digital signal generator based on MCU, can produce sine wave. Triangular wave)

uart_tr 异步串口通信主机 使用verilog HDL语言编写(uart_tr the host of the uart )

一种基于格雷码的异步FIFO设计与实现,8*8位的fifo VHDL 源码-Gray-code based on the Asynchronous FIFO Design and Implementation

二进制转十进制BCD码 Verilog语言 quartusII(Binary to decimal BCD code Verilog language quartusII)

The AGC is a smart programmable gain amplifier (PGA). The amplifier gain is adjusted based upon the input signal level so that the output is at a specified Target Gain. The AGC can be configured to be either a mono or stereo input / output component. For illustration purposes, the following discussion will highlight the stereo configuration.

turbo码的verilog程序，有意者请下载。(turbo code verilog procedures Interested parties please download.)

VHDL黄金参考手册，能让你更好的学习了解VHDL语言(VHDL gold reference manual, can make you a better learn VHDL language)