基于CPLD的签到器的设计，用三维数组队人名进行储存

EDA常用双LED显示译码程序，将四位二进制数译码为七位对应于LED7位输入的高低电平信号-EDA common dual LED display decoding procedure will be four binary decoding for seven LED7 spaces corresponding to the input signal circuits

fpga的一个小程序用于3s500e 4*4键盘模块(fpga is a small program used 3s500e 4* 4 keyboard module)

---实现的部分VHDL 程序如下。 　　--- elsif clk1x event and clk1x = 1 then ---if std_logic_vector(length_no) >= “0001” and std_logic_vector(length_no) <= “1001” then -----数据帧数据由接收串行数据端移位入接收移位寄存器---rsr(0) <= rxda --- rsr(7 downto 1) <= rsr(6 downto 0) --- parity <= parity xor rsr(7) --- elsif std_logic_vector(length_no) = “1010” then --- rbr <= rsr --接收移位寄存器数据进入接收缓冲器--- ...... --- end if(--- achieve some VHDL procedure is as follows.--- Elsif clk1x event and then a clk1x = s--- if td_logic_vector (length_no))

stepper motor module on spartan 6 and 24MHz clock fequency

基于BCD码的十进制ALU设计，可实现加减乘除的功能(BCD to decimal ALU based design can achieve the arithmetic function)

在图像中

增强型8051的VHDL源代码，两个周期执行一条指令，仿真工具为Modelsim，开发板为Altera的EP1C20开发板-enhanced 8051 VHDL source code, the implementation of a two-cycle instruction, simulation tools for Modelsim, development board for the Altera EP1C20 development board

无刷直流电机 VHDL VERILOG 控制,速度环，RS232 串口接收发送 始终分频 PWM生成 电机相序 actel FPGA使用-VERILOG BLDC control of the use of actel FPGA( actel VERILOG BLDC control of the use of actel FPGA)

基本的usb驱动程序的编程方法,值得一看.-Basic programing method for USB driver, worth reading

此压缩包里面有基于vivado平台的工程，包括了正弦信号的产生，还有fir滤波器的设计以及fft算法的设计实现(in this package,there are three projects of the generation of the signal of sin and the design of fir filter and the ari)