11阶滤波器的verilog编程语言，可很好的实现滤波功能。

适用于NIOS II的1024点FFT C算法( 1024-point FFT C algorithm for NIOS II)

基于小波变换去噪，采用了vhdl编写，已经在和matlab上对比过，结果准确，而且大量的节约了时间，欢迎下载，可以在quartusii中查看RTL电路，可以在modesim中仿真出结果

一个用VHDL编写的跑马灯程序和60进制计数器的程序，一个是自己设计的一个是老师要求，都在实验箱上验证成功，希望对大家有所帮助。-Marquee with a program written in VHDL, and 60 binary counter program, one designed by one teacher asked, are in the experimental boxes proved to be successful, want to help everyone.

实光电码盘的输出数据的四倍频，使码盘输出精度提高四倍。-real photoelectric encoder output data of the four frequency, accuracy encoder output increased by four times.

design ram v8051 for project

通过正弦波和三角波的比较产生SPWM波形(Through the comparison of sine wave and triangle wave produces SPWM waveform)

16X2液晶显示屏的FPGA显示驱动设计。-16x2 LCD display driver design of the FPGA.

用VHDL实现十六位移位乘法器 才有移位相加法来实现-Use VHDL to achieve 16-bit shift multiplier shift only the sum of law to achieve

基于sopc的7352的ad模块的nios软核多通道编写,verilog 写的(The sopc 7352 AD module nios soft core multichannel write. Rar )

code for kcpcm3 : Describes the working of KCPCM3 embedded in picoblaze xilinx-code for kcpcm3 : Describes the working of KCPCM3 embedded in picoblaze xilinx