7485比较器

说明：  4位加法器，4位数字相加及进位功能的实现，主要利用Verilog语言实现，简单轻松，且代码量少(a adder which can realize 4 bit numbers adding)

verilog写的数字频率计的显示模块,可以-written in Verilog Digital Cymometer display module can be

-- State machine for reading data from Dallas 1621 -- -- Testsystem for i2c controller--- State machine for reading data from Dall as 1621---- Testsystem for i2c controller

EDA设计实验，用VHDL编写的数字时钟代码，能显示分，秒，小时。根据所设置的频率不同，能够调整时间快慢。-EDA design of experiments, prepared by VHDL code digital clock showing the hours, seconds, hours. According to the frequency of different settings, time to adjust speed.

说明：  对fpga的学习有一点帮助，属于较为基础的部分(It has a little help to the study of FPGA, which belongs to the more basic part)

verilog 语言写的FPGA内部实现硬件浮点乘法器的源码，两个时钟周期完成一次浮点乘法运算(The FPGA language written in Verilog implements the source of the hardware floating point multiplier, and completes the floating point multiplication operation in two clock cycles.)

拿verilog编写的som(自适应神经网络算法)，用于障碍物检测，基于FPGA可综合实验，已经在altera的cylcone上实现(Canal verilog prepared som (adaptive neural network algorithm) for obstacle detection. Based on FPGA synthesis experiments, in altera achieve the cylcone)

ethernet 10 0M MAC-ethernet MAC 10,100 M

高级FPGA设计__结构、实现和优化,中文翻译版(Advanced FPGA Design- Architecture, Implementation, and Optimization)

ADC Reference code!Clock 100kHz