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11_rs485_uart_top
说明: verilog编写的RS485读写驱动程序(RS485 read-write driver written by Verilog)
- 2020-03-08 12:28:10下载
- 积分:1
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half_adrrrrder
FPGA上的一个半加器实例程序,通过测试,可以直接运行在fpga开发板上。(One and a half adder example on FPGA program, through the test, can be run directly on the FPGA development board)
- 2013-12-01 12:01:31下载
- 积分:1
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基于FPGA控制的DDS波形发生器
基于FPGA控制的DDS波形发生器,可在Cyclone IV系列板子上使用,已经过仿真验证(Based FPGA control DDS waveform generator in Cyclone IV series board on use, has been simulation)
- 2017-03-17 11:08:39下载
- 积分:1
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016_versat_updown_counter
说明: Verilog实现的加减法功能计数器,通过独立的自增自减信号控制计数器进行自增计数和自减计数(Function counter of addition and subtraction implemented by Verilog)
- 2019-11-27 23:16:27下载
- 积分:1
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CDCM6208_SPI
说明: 完成对cdcm6208的时钟芯片的配置,输出高频时钟(cdcm6208 cofigure using SPI interface)
- 2021-02-06 18:29:56下载
- 积分:1
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VHDL描述的时钟分频电路,用途广
VHDL描述的时钟分频电路,用途广-VHDL description of the clock divider circuit, uses widely ...
- 2022-03-10 15:35:57下载
- 积分:1
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TOFED_TB_1
A 4 bit twisted ring counter is a sequential circuit which produces the following sequence of
output values: 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001 and then repeats. Design a
circuit for a 4 bit twisted ring counter that uses four D flip flops. Draw a state transition
diagram, a state table and a schematic for your circuit. Design an alternate implementation
using just three flip flops and draw a state transition diagram, state table and a schematic
for your circuit. If your designs are extended to implement an n bit twisted ring counter,
how many flip flops are required using each of the two approaches. In what situations
would you prefer the first method? In what situations would you prefer the second?
- 2014-11-08 06:58:55下载
- 积分:1
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VHDL_programs
VHDL programmes for basic digital circuits. begineers can learn easily
- 2013-09-28 13:46:58下载
- 积分:1
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BLUE
说明: 利用EGO1数模混合口袋实验平台上的蓝牙模块与板卡进行无线通信。使用支持蓝牙 4.0 的手机与板卡上的蓝牙模块建立连接,并且通过手机 APP 发送命令,控制 FPGA 板卡上的硬件外设。(The Bluetooth module on the EGO1 digital-analog mixed pocket experimental platform is used to communicate with the board. The Bluetooth 4.0-enabled mobile phone is used to establish a connection with the Bluetooth module on the board, and commands are sent through the mobile phone APP to control the hardware peripherals on the FPGA board.)
- 2020-06-24 02:00:02下载
- 积分:1
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fsm
有限状态机工作原理、设计方法、步骤等精要说明(Finite state machine working principle, design method, such as Essentials of steps to explain)
- 2010-02-13 17:46:25下载
- 积分:1