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FPGA
zc706板子原理图,在使用板子时候可以参照设计,使用帮助巨大。(Zc706 board schematic diagram, when using the board can be reference to design, use the help.)
- 2016-01-13 22:00:05下载
- 积分:1
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yibuqingling
含异步清零和同步清零的计数器的设计,内容是源代码,以及相关文件,打开即可(Clear cleared asynchronous and synchronous with the counter design, content source code and related documents, can be opened)
- 2011-08-24 10:44:33下载
- 积分:1
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VHDL的初学者可以参考此VHDL加法器,相信会给你带来不小的收获...
VHDL的初学者可以参考此VHDL加法器,相信会给你带来不小的收获-VHDL beginner can refer to the VHDL adder, I believe will bring you not a small harvest
- 2022-05-20 03:51:48下载
- 积分:1
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用于压缩感知。OMP 是一种算法
用于压缩感知。OMP 是一种算法
- 2023-04-30 08:30:04下载
- 积分:1
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QPSK_System
实现QPSK系统的调制解调仿真,基带成形滤波器采用升余弦滚降滤波器,将仿真的误码率与理论误码率作了比较(Implement QPSK modulation and demodulation simulation system, the baseband shaping filter using Raised Cosine filter will BER simulation were compared with the theoretical BER)
- 2020-12-22 15:39:07下载
- 积分:1
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led1
说明: 点亮led流水灯,通过调用锁相环,可以更改对应的时钟。(Lighting the LED pipelining lamp, the corresponding clock can be changed by calling the phase-locked loop.)
- 2020-06-16 07:00:01下载
- 积分:1
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scramble
基于VHDL实现加扰器解扰器的设计,与仿真。(VHDL-based scrambler descrambler design and simulation.)
- 2013-01-11 20:15:54下载
- 积分:1
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jianpan
说明: 一个简单的键盘接口模块程序,对键盘输入的数据和时钟信号进行过滤。过滤后的数据信号PS2Df将被送入两个11位移位寄存器中(A simple keyboard interface module program filters keyboard input data and clock signals. The filtered data signal PS2Df will be fed into two 11-bit displacement registers.)
- 2020-06-24 02:00:02下载
- 积分:1
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ISE7.1i 中文教程 适合xilinx的FPGA/CPLD用户
ISE7.1i 中文教程 适合xilinx的FPGA/CPLD用户-Chinese ISE7.1i the xilinx tutorial for FPGA/CPLD users
- 2022-02-25 00:06:16下载
- 积分:1
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sdram controller vhdl
sdram controller vhdl
- 2022-03-11 14:56:59下载
- 积分:1