vhdl的一个串行序列信号发生器的设计与实现

hi this is an verilog codes

FPGA简单VGA彩条显示程序驱动程序640*480(FPGA simple VGA color display Driver 640* 480)

cycloneII Quartus verilog开发的简单时序电路-cycloneII Quartus verilog to develop a simple sequential circuit

一个异步FIFO的verilog实现论文-err

FPGA流水线设计的资料，可以作为学习FPGA开发并行操作的一个经典教材，具有很好的指导作用。(FPGA pipeline design information can be developed as a learning FPGA parallel operation of a classic textbook, has a good guide.)

基于OV7670采集，SDRAM缓存，sobel处理，VGA显示的工程，内有全部代码，基于QUARTUS开发板实现。 FPGA 边缘检测(Based on OV7670 acquisition, SDRAM cache, sobel processing, VGA display project, with all the code, based on QUARTUS development board. FPGA edge detection)

基于vhdl可用的数字频率计，误差较小，精准度较高。文件中还包含了与arm的通信模块、

同步fifo的调用程序，调用Quartus II 9.0 (32-Bit)中的fifo模块(Synchronous fifo calling program, call Quartus II 9.0 (32-Bit) in fifo module)

改自特权同学verilog语言写sdram测试程序；支持256M内存(verilog sdram )

An FSM using VHDL and Johnson state encoding for states