华为_大

spartan6 里使用DDR3IP核，有教程以及源码(spartan6 with ddr3,source and tutorial)

DAC0832 接口电路程序.功能：产生频率为762.9Hz的锯齿波DAC0832VHDL程序与仿真-DAC0832 procedures interface circuit. Functions: generate the sawtooth frequency of 762.9Hz and simulation procedures DAC0832VHDL

用VHDL写的交通灯控制源码，原创，希望对大家有所帮助-Use VHDL to write a traffic signal-controlled source, originality, and they hope to help everyone

FPGA锁相环实验： 顶层文件加底层IP文件构成 top中例化ip核pll(Experiment of Phase-Locked Loop Based on FPGA)

一位加法全加器，可以实现低位进位输入和高位进位输出。(full adder)

AD转换的Matlab程序，将输入电压转换成时间(脉冲宽度信号)或频率(脉冲频率)，然后由定时器/计数器获得数字值(AD conversion of the Matlab program, the input voltage is converted into a time (pulse width signal) or a frequency (pulse frequency), and then to obtain a digital value by the timer/counter)

可配置CRC参考设计 xilinx提供的VHDL-configurable CRC reference design for Xilinx VHDL

LDPC encoding code in 1/2code rate for DVB-T2

writing testbench in system verilog

verilog实现的“六进制约翰逊计数器”。-verilog implementation of the " six hexadecimal Johnson counters."