华为_大

北大verilog课件，数字集成电路设计入门，从HDL到版图-North Verilog courseware, digital IC design entry, from HDL to the map

加减可控制的十到十六进制计数器。完全准确，可以放心使用的(Add and subtract controllable ten to hexadecimal counter. Entirely accurate, can be at ease of use)

本文件是可以直接使用下载到FPGA里面使用，里面包含时钟分频电路，串并转换和并串转换电路，多通道信号加权的乘加电路等。-The document may download to FPGA chip to complete the clock divider,serial-to-parallel,parallel-to-serial,and multiple-add circuit for multiple channels weight calculation

this a vhdl code for usb-this is a vhdl code for usb

vga接口的工程实现，基于altera环境，需要的可以-vga interface engineering implementation, based on altera environment, need to take a look at

vhdl学习方法,含有大量的vhdl源代码,对vhdl的语法的介绍-VHDL source习laugh Yang, Yi bleed at the nose cavity submerged stresses measured tungsten Daitou VHDL, VHDL-Qin Pang Yang cavity cavity Geng Zhuang

altera公司飓风四代芯片，LCD屏幕彩条显示，有效实现行、场扫描。练习FPGA驱动VGA或LCD显示的入门程序(Altera hurricane four generation chip, LCD screen color display, the effective realization of line and field scanning.Practice FPGA to drive VGA or LCD display)

FPGA控制m25p16flash芯片读写控制spi协议 可实现擦除写入读出功能(SPI protocol for read and write control of m25p16 flash chip controlled by FPGA Erase Write-Read Function)

基于sopc的lcd时钟，开发工具为nios ii和quartus ii9.0(Based on sopc the lcd clock, development tools for the nios ii and quartus ii9.0)

A controller for DDR2 on FPGA with vhdl, content testbench, model and textfile-generation/data-detection using python.