The document may download to FPGA chip to complete the clock divider,serial

Verilog的135个经典设计实例.使你工作使用学习中，会有很大帮助，各种典型案例(135 classic Verilog design examples. Make your work with the study, will be of great help, of various typical cases )

说明：  有关risc-v cpu的问题,里面有一些有关cpu的设计(The problem of risc-v can be solved)

无线通信FPGA实现的代码 有matlab和verilog(FPGA implementation of wireless communication code matlab and verilog)

用verilog语言实现了tlk2711serdes芯片的高速串行功能，包含工程与仿真文件，亲测可用(Using Verilog language to achieve a high-speed serial tlk2711serdes chip function, including the project and the simulation file, pro test available)

ip核的FFTverilog源代码，说明不是很具体-ip nuclear FFTverilog source code, that is not very specific

说明：  CC217编程序，verilog实现，串行输入串行输出(CC 217 program, to achieve Verilog, serial input serial output)

LDPC的编码模块和解码模块，实现802-3an协议的编码(The module of LDPC to implement the coding of the 802-3an protocol)

VerilogHDL.自动增益控制模块中产生控制电压的部分-VerilogHDL. Automatic Gain Control Module have some control voltage

同步串行数据发送电路SSDT的基本功能是将并行数据转换成串行数据并进行同步发送。系统写入和读出时序完全兼容Intel8086时序。 系统以同步信号开始连续发送四个字节，在发送中出现5个1时插入一个0，在四个数据发送结束而下一次同步没有开始之前，发送7FH，这时中间不需要插入零 -synchronous serial data transmission circuit SSDT the basic function is to convert parallel data into serial and the same this step. System write and read sequential fully compatible Intel8086 timing. Synchronized signal system to start sending four consecutive bytes, in this emerging 5 1:00 insert a 0, at the end of four data sent and the next synchronization not started before, sending seven FH, then the middle is not inserted

很多VHDL例子，没有测试，供大家参考-VHDL many examples, there is no test, for your reference