vga接口的工程实现，基于altera环境，需要的可以

FPGA与DAC芯片的SPI接口驱动，实现串行数据的传输。(Realizing the communication between FPGA and DA chip)

Use serial programming examples matlab GUI implementation, Independent component analysis for image processing, Realize image watermarking, de-noising, plus noise and other functions.

在quartus软件下用VHDL语言实现DDS，可产生正弦，余弦，方波，三角波以及锯齿波。-In the Quartus software using VHDL language realize DDS, can generate sine, cosine, square, triangle and sawtooth waves.

single cycle mips design by verilog.

FPGA经验总结：时序是设计出来的 我们在做详细设计的时候，对于一些信号的时序肯定会做一些调整的，但是这种时序的调整最多只能波及到本一级模块，而不能影响到整个设计。(FPGA Experience: Timing is designed to do the detailed design of our time, for some signal timing will certainly make some adjustments, but adjust this timing can only spread to up to this level of the module, but not affect the whole design.)

this files in Quartus2 are fulladder

ahb总线Verilog代码及sv仿真文件(ahb bus Verilog code and sv simulation code)

十进制精确计数，经典写法，便于学习与参考，供大家分享-Decimal precision counts, classic written, easy learning and reference for all to share

2011年 电赛 E题 简易数字信号传输性能分析仪FPGA信号发生部分 包括m序列，伪随机序列，曼彻斯特编码 程序 和单片机部分程序(2011 CEC E title simple digital signal transmission performance analyzer FPGA signal part of the program and single-chip part of the program)

按键控制LED流水灯；按键1按下前8个灯从左到右依次点亮，按键2按下中间前8个灯从左到右依次点亮，按键3按下所有灯全亮(Water control button LED lights sequentially lit buttons the eight lights left to right 1 Press button 2 press from left to right is lit in the middle eight lights, key 3 Press All full bright light)