用VerilogHDL进行频率生成器。

class diagram diagram for AIRS

脉冲宽度调制，VHDL代码编写，包括QUARTUSII和MODELSIM工程以及testbench-Pulse width modulation, VHDL coding, including QUARTUSII and ModelSim engineering and Testbench

VIP FPGA板的配套例子，这个是VGA格式lcd液晶屏幕显示用。(VIP board supporting example of this is the VGA format PREVIEW.)

MATLAB Filter Design HDL Coder Simunlink HDL Coder Xilinx ISE Webpack

4人抢答系统，可以计时20秒，20秒无人抢答则视作无人抢答。start之前抢答者视为违规抢答，违规抢答会警告选手。若有一人抢答则其他3人锁定，不可再抢答。aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa

verilog实现DLX指令集5段流水线(5 stage DLX pipeline implemented in verilog)

清华大学电子课程设计：Verilog，QuartusII可正确运行，可下载到FPGA上，完成远程通信的整体任务，PC发数据，键盘输入运算符与运算数计算将结果显示在数码管上并返回给PC机，需异步串口调试软件(Verilog, QuartusII run correctly, can be downloaded to the FPGA, to complete the overall task of remote communication, PC send data, keyboard operators and operands calculation displays the results in digital tube and returned to the PC, to be asynchronous serial debugging software)

一个简单移位寄存器代码，verilog HDL编写(a simple shift register example，write with verilog HDL)

乒乓球游戏，用led灯控制水上乒乓球，选择了控制键进行操作。详细信息请参见自述