用VerilogHDL进行频率生成器。

此示例是8051核加频率计的联合设计,带有8051IP核资料-This example is the 8051 nuclear increase the frequency of joint design, with the nuclear information 8051IP

表决器，简单实现了表决功能，无显示功能 -vote

yong VerilogHDL yu yan bianxie de pinlv fa sheng qi,shi yong ISE ruan jian da kai.-Used VerilogHDL to make a frequency builder.

VIVADO 从此开始,详细讲解了vivado,FPGA开发工具的使用，对于初学者学习VIVADO工具很有用。(VIVADO from now on, explained in detail the use of vivado, FPGA development tools, for beginners to learn VIVADO tools very useful.)

例如分频器，alu，ram的verilog实现(The implementation of divider, alu, ram etc. in verilog)

用verilog编写的包含有与DSP通信，三电平svpwm实现的程序，(Written in verilog contains communicate with the DSP, three-level svpwm realize the procedures)

SMbus通讯协议的Verilog程序段，已通过Moldesim的仿真，可用(Verilog program segment of the SMbus communication protocol, has been through the Moldesim simulation, the available)

AGC(自动增益放大) Verilog代码 设计可以参考 第二部分(AGC (automatic gain control) can refer to the Verilog code design )

在开发板EGO1上实现的直升机飞行游戏，随时间的累积，速度不断加快，数码管显示积分( Helicopter game in verilog)

以太网的FPGA程序实现以太网的FPGA程序实现以太网的FPGA程序实现(enternet verilog fpga)