CPLD总线Verilog HDL代码，PLD

simple microprocessor that gives the greatest common divisor of 2 (4bit) numbers

spartan605评估板测试代码。xilinx官方资料(spartan605 uation board test code)

Cadence_manual_1.2.pdf

基于quartus的3-8译码器,可作为大型系统的译码器模块-Based on quartus a 3-8 decoder can be used as large-scale system decoder module

verilog入门基础以及简单编程介绍，verilog是近几年发展迅速的一门硬件语言-Verilog entry basis, as well as introduce a simple programming, verilog in recent years the rapid development of a hardware language

Vhdl实用教程，可帮助初学者迅速掌握VHDL的编写-Vhdl practical tutorials to help beginners to grasp quickly the preparation of VHDL

Spartan 3 Digilent Demo:This demo drives the perphrials on the Spartan 3 board. This drives a simple pattern to the VGA port, connects the switches to the LEDs, buttons to each anode of the seven segment decoder. The seven segment decoder has a simple counter running on it, and when SW0 is in the up position the seven segment decoder will display scan codes from the PS2 port. This demo how ever does not drive the RS-232 port or the memory. This is a simple design done entirely VHDL not microblaze.

辛辛苦苦的作品应用于DE2 的 开发。。希望对大家有用。-hard work for Dictyophora development. . We hope that the right useful.

通过神经网络实现的PID算法，整个工程文件，调试通过。(By PID algorithm neural networks, the entire project files, debugging through.)

System Generator