CPLD总线Verilog HDL代码，PLD

运用vhdl硬件描述语言在quartus II开发环境下独立设计与实现了基于精简指令集的五级流水线CPU的设计与实现。该流水CPU包括：取指模块，译码模块，执行模块，访存模块，写回模块，寄存器组模块，控制相关检测模块，Forwarding模块。该CPU在TEC-CA实验平台上运行，并且通过Debugcontroller软件进行单步调试，实验表明，该流水线CPU消除了控制相关、数据相关和结构相关。(Using vhdl hardware description language development environment under quartus II design and implementation of an independent design and implementation of a five-stage pipeline RISC-based CPU' s. The water CPU include: fetch module, decoding module, execution modules, memory access module, the write-back module, the register set of modules, control relevant to the detection module, Forwarding module. The CPU in the TEC-CA experimental platforms, and single-step debugging through Debugcontroller software, experiments show that the pipelined CPU eliminates the control-related, data-related and structurally related.)

用VHDL编写的串口通讯程序，包括几个不同的程序例子，也可以用verilog进行改写。()

OFDM modulation source code written in Matlab

基于FPGA的local bus接口。包含基于fifo和普通寄存器的两种方案。(FPGA-based local bus interface. Based fifo contains two programs and the general register.)

利用ANSYS有限元仿真软件对复合材料进行异常检测仿真实验，程序为一损伤样板模型(ANSYS finite element simulation software for composites simulation anomaly detection, the program is a damage model model)

RISC-DSP组合处理器设计优化[1].-RISC-DSP processor design portfolio optimization [1].

如果需要用verilog设计一项比较简单的功能，那么这个浅显易懂的程序能让你很快明白点阵的设计方法，尤其是对那些初学者(If you need to use a relatively simple verilog design features, then this easy to understand design of the program allows you to quickly understand the lattice method, especially for those who are beginners)

This is the update firmware for CVFX-C02, 7" motorized touch screen car dvd player gps

Verilog实现的USB程序，用ISE打开工程文件即可-Verilog implementation USB program, open the project file with the ISE can be

基于FPGA编写的verilog代码，在xilinx上仿真实现FFT变换(FPGA-based verilog code written in xilinx FFT transform Simulation)