Xilinx公司Accel DSP项目

vhdl code for decoder and detemines the basic mechanism of gates of decoder

Verilog HDL教程 什么是Verilog HDL？ Verilog HDL 硬件描述语言(What is a Verilog HDL tutorials Verilog HDL? Verilog HDL hardware description language)

完成cmos摄像头对图像的捕捉，然后进行拼接通过USB进行传输。(complete picture capture)

one of example about hardware design language

pngenerator的vhdl代码。我们可以在cdma的fpga实现中使用它；

QUARTUSII 9.0 下的三级流水线中值滤波工程，vhdl源程序等。可用于fpga做图像预处理。(the three stage pipeline median filter project under QUARTUSII 9 , VHDL source program. which can be used by FPGA to do image preprocessing. )

fpga程序，产生1pps脉冲信号，使用的verilog语言。(FPGA program generates 1 PPS pulse signal, using Verilog language.)

用Hspice实现一个三输入异或门，并分析其功耗和延时。(A three input XOR gate is implemented by Hspice, and its power consumption and delay are analyzed.)

采用双线性变换法设计IIR数字滤波器设计的c代码，包括低通、高通和带通(Document recording the design of IIR digital filter c code)

这是一个基于车租车计费器的模拟计算系统，用VHDL语言实现(This is a car rental billing based on the simulation system, using VHDL language)