Xilinx公司Accel DSP项目

bt1120设计方案，描述了具体的方案设计以及整体的架构设计(Bt1120 design scheme, describes the specific scheme design and the overall architectural design)

本例程使用vivado2014.4工具，利用xilinx Basys3 实验板实现板载流水灯的两种模式控制。(This project uses verilog HDL to realize the the control of 16 leds loaded on Xilinx Basys3 board.)

32位元浮点CPU,用VHDL语言以类似组合语言的方式写成-32 floating-point CPU(VHDL)

存储示波器，功能齐全通过验证，毕业设计用-Storage oscilloscope, a full-featured validated, graduation design

扰码器的verilog实现,参考802.11a相关标准-Scrambler in verilog implementation

利用VHDL实现CPLD（EMP240T100C5）的PWM输出-Using VHDL realize CPLD (EMP240T100C5) of the PWM output

CPLD imlementation of I2C BUS Controller. The description has been made by VHDL

altera推出的基于它们fpga和cpld的构建嵌入式系统的新技术sopc的介绍。其集成在quartus II中-ALTERA due to launch them and they simply cpld Construction of the new Embedded System Technology sopc briefing. Its integrated into the Quartus II

verilog code for apb to ahb convert

基于FPGA的DM9000A芯片的网络数据采集系统，基于NIOS架构，c语言编程，资料齐全，包含不止5个源程序，绝对受用！(FPGA-based the DM9000A chip network data acquisition system based on NIOS architecture, c programming language, the information is complete, contains more than 5 source code is absolutely good enough!)