VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

MPSK调制与解调VHDL程序源代码与仿真(MPSK modulation and demodulation process and VHDL source code and simulation)

利用matlab提供的firhalfban函数设计阶数为16、通阻带容限为0.0001的半带滤波器。仿真测试滤波前后的信号时域图，回执滤波器的频率响应特性图(Provided firhalfban function using matlab design order of 16, through the 0.0001 stopband wool half-band filter. Simulation test filtered time domain signal before and after, receipt filter frequency response characteristic diagram)

基于fpga的verilog实现ad及uart，并进行仿真验证(Verilog based on FPGA implements AD and uart, and carries out simulation verification)

VHDL版的C51核(MC8051)-VHDL version of the C51 core (MC8051)

按键控制数码管显示，从0到9显示，八位数码管(Button control digital tube display)

设计要求1） 每帧数据供 10 位，其中 1位启动， 8位数据， 1位 停止。2） 波特率为： 9600 。3） 收发误码率

pid算法控制电机运动，实现fpga与dsp的双口RAM通信(PID algorithm to control motor movement, the realization of FPGA and DSP dual port RAM communication)

说明：  VHDL BISS,SSI,ENDAT2.2, ENCODER

在BASYS3上实现跑马灯的功能。第一LED交替闪烁；第二LED由左至右逐个变亮，再逐个变暗；第三LED由右至左逐个变亮，再逐个变暗；第四LED由两边逐个变亮，再从中间逐个变暗。(Realize the function of the horse light on BASYS3. The first LED flashes alternately; second LED brightens from left to right and then darkens one by one; the third LED turns from right to left, then darkens one by one, and then darkens one by one; fourth LED is brightened by both sides, and then darkening from the middle.)

说明：  利用vhdl语言编写的译码器程序，采用两种不同方式(The use of language decoder vhdl program, using two different ways)