VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

useful VHDL document for programmer

此代码能够使得键盘控制液晶，实时的进行书写，按下Backspace清屏(This code enables the keyboard to control the LCD, in real-time writing, press Backspace clear the screen)

在MATLAB下自编实现快速傅里叶分析，(Fast fft own procedures, faster than the system call fft slowe)

VHDL语言的cookbook,能够使你更快的学会使用VHdL-cookbook

使用vriloge硬件描述语言设计数字频率计，其对于高频测量精确，可测范围0―99999999HZ，在MAX+PLUSII中运行通过并在实验箱上运行通过达到要求-The use of hardware description language design vriloge digital frequency meter, and its high-frequency measurement for accurate, range 0-99999999HZ, in MAX+ PLUSII run me through and run the experiment to meet the requirement through

OMAP5912 UART的测试程序 包括头文件 源文件等。(OMAP5912 UART program test)

四轴动力模块，用一个顶模块控制，输入有：油门（20档）；指令；水平仪控制指令，4个输出口(Axis power modules, with a top module control inputs are: accelerator (20 files) instruction Level control instructions, four output ports)

SOC Verfication Methodology and Techniques

通过总结当前对处理器架构的安全性能的处理方法，提出一种增强DSP处理器安全性能的方法。主要从并行性方面进行了改进。最后对改进的方法进行了仿真和结果分析。(By summing up the current security architecture of the processor performance approach, a DSP processor to enhance the safety performance of the method. Mainly from the aspects of parallelism to improve. Finally, improved methods and results of simulation analysis.)

quartus 中，高级io分配，手动的例子-Quartus senior io distribution, manual example