VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

基于cordic算法的DDS的Verilog代码。经过仿真验证，绝对可靠。(Based on cordic algorithm DDS Verilog code. Through the simulation, is absolutely reliable.)

简单介绍了直接数字频率合成技术(DD S)，利用DDS设计任意 波形发生器，其能够产生矩形波、正弦波、三角波、锯齿波等多种波形 -A brief introduction of direct digital frequency synthesis (DD S), the use of DDS design of arbitrary waveform generator, which can produce rectangular wave, sine wave, triangle wave, sawtooth waveform etc.

FPGA的卷积编码小程序，VHDL描述，参数为2，1，7.(2,1,7 cov with VHDL.)

SDRAM控制器源码，内含完整的控制器verilog源代码和测试代码，超值哈。(This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1.)

基于FPGA的pci总线接口设计。。。。。。。。。。。。。(FPGA-based PCI bus interface design)

quartus II 13.0 DDS工程文件，采用VHDL编写，可输出正交两路正弦信号。可以直接用modelsim-alter 仿真(quartus II 13.0 DDS project file, using VHDL written two orthogonal sinusoidal output signals. Can be simulated directly modelsim-alter)

A Full adder using half adder unit in vhdl

FPGA KIT DE2-35 This project outputs a selected voltaje using VGA DAC, the DAC module is controlled using LCD display and buttons.

In this case is a QPSK algorithm code for mapping the interleaved code, using VHDL language. This code provide the method of mapping the code by using QPSK algorithm.

对NC Verilog的基本介绍，详细的图解，非常适合初学者使用，一个word文档和一个pdf文档-NC Verilog on the basic introduction, detailed diagrams, very suitable for beginners to use, a word document and a pdf document