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基于FPGA的乐曲发生器电路设计 附含源代码(quartersii环境下运行)...
基于FPGA的乐曲发生器电路设计 附含源代码(quartersii环境下运行)-FPGA-based circuit design of the music generator containing the source code is attached (quartersii environment to run)
- 2022-02-16 04:27:54下载
- 积分:1
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vhdl
说明: 这个事VHDL基础知识,内面主要内容是编码器的插V过程,值得下载学习!(it is really useful for those who never touch it!)
- 2010-04-16 13:57:35下载
- 积分:1
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xilinx of ddr sdram controller documentation
xilinx的ddr sdram控制器文档-xilinx of ddr sdram controller documentation
- 2023-04-17 06:40:03下载
- 积分:1
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GW48系统电子琴:可控制8个音节,4种音调 readme中带使用说明
GW48系统电子琴:可控制8个音节,4种音调 readme中带使用说明-GW48 system : control eight syllables, four species of taking the pitch readme use
- 2022-05-21 12:22:34下载
- 积分:1
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等精度频率计的verilogHDL的实现,我花了好长时间才写的哦
等精度频率计的verilogHDL的实现,我花了好长时间才写的哦
- 2022-06-28 09:27:01下载
- 积分:1
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cordic
CORDIC(Coordinate Rotation Digital Computer)算法即坐标旋转数字计算方法。 CORDIC算法,能够通过平移和累加快速实现基础的数学函数,包括三角函数,开方,指数,对数,平方根等函数。(CORDIC (Coordinate Rotation Digital Computer) algorithm for the coordinate rotation digital calculation. CORDIC algorithm can be achieved through the rapid translation and accumulation based on mathematical functions, including trigonometric, square root, exponential, logarithmic, square root and other functions.)
- 2020-06-29 13:40:02下载
- 积分:1
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shumaguandongtai
VHDL的动态扫描显示六个数码管,包含分频代码产生25kHz的扫描信号作为时钟。(VHDL dynamic scanning display six digital tube contains 25kHz scanning signal is generated as a clock divider code.)
- 2012-11-26 14:40:42下载
- 积分:1
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frenqucy
利用康芯公司的FPGA芯片设计制作频率计,实现对频率的测量。(Kang core using FPGA chip design company frequency meter, realize the frequency measurements.)
- 2011-07-27 15:49:30下载
- 积分:1
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Xilinx公司Accel DSP项目
xilinx accel dsp实例项目工程-xilinx accel dsp project
- 2023-03-09 20:10:02下载
- 积分:1
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vhdl,序列信号检测模块,此模块检测1110010,可改为任意序列,输出电位为1为检测出,否则为0...
vhdl,序列信号检测模块,此模块检测1110010,可改为任意序列,输出电位为1为检测出,否则为0-vhdl, sequence of signal detection module, this module testing 1.11001 million, can be changed to an arbitrary sequence, the output potential of an as detected, otherwise 0
- 2022-10-12 22:25:03下载
- 积分:1