计数器，用VHDL语言实现。

对aurora模块时钟处理模块，实现时钟的分频等处理(Aurora module clock processing module,Clock frequency division and other processing)

基于FPGA的i2s接口输入模块设计，其中有原理图和verilog源码，可在Quartus环境下进行仿真(FPGA-based i2s interface input module design, including schematics and verilog source code, can be simulated in Quartus environment)

10进制计数器，VHDL描述的，实验必备-10 hexadecimal counters, VHDL description of the experiment must

9对于输入密码锁的键，假设复位后七个灯显示" 0"，使用sw1、sw2、sw3、sw4 4，只需按下并松开任意sw1、sw2键，使七个灯显示值加" 1"，只要按下并松开任意sw3、sw4，将使七个灯显示值加" 2"

synopsys的systemc和RTl书籍清晰电子版，专业权威的EDA公司的培训资料(synopsys of systemc and RTl clear electronic version of books, professional authority of the EDA company' s training materials)

very much verilog code for the beginner

说明：  FPGA实现基带成型滤波器，升余弦滚降系数，多进制调制(FPGA)

俩个比较好的计数器的vhdl代码：一个是n位通用计数器，一个是的用到的语法比较全面。是比较好的学习资料-Both a relatively good counter VHDL code: one is the generic n-bit counter, one is the syntax used in the more comprehensive. Is a better learning materials

VHDL源码 VHDL源码 -VHDL source VHDL source VHDL source

说明：  数字信道化过程中多相滤波器组matlab代码及测试(Digital channelized polyphase filter code and test)