135个经典VerilogHDL源码和说明文档，入门的好资料

verilog_ad0809 cpld control

7段数码显示译码器设计7段数码是纯组合电路，通常的小规模专用IC，如74或4000系列的器件只能作十进制BCD码译码，然而数字系统中的数据处理和运算都是二进制的，所以输出表达都是十六进制的，为了满足十六进制数的译码显示，最方便的方法就是利用译码程序在FPGA/CPLD中来实现。例子作为七段译码器，输出信号LED7S的7位分别接数码管的7个段，高位在左，低位在右。例如当LED7S输出为“1101101”时，数码管的7个段g、f、e、d、c、b、a分别接1、1、0、1、1、0、1；接有高电平的段发亮，于是数码管显示“5”。-7 digital display decoder design 7 Digital is pure combinational circuits, usually of small-scale dedicated IC, such as 74 or 4000 Series devices can only be used to decimal BCD decoder, but digital systems in the data processing and computing are binary, so the output expression are hexadecimal, and hexadecimal number in order to meet the needs of the decoding shows that the most convenient way is to use decoding process in FPGA/CPLD in to achieve. Seven-Segment decoder as an example, the output signal of the seven were LED7S access digital pipe 7 above, high in the left, low in the right. For example, when LED7S output as

IT8051，增强版的T51，兼容DW8051核的多数端口，IO需要扩展后使用

this fpga spartan 3e based project file .the project is the game based on vga. this file contains 2,20,25,400Hz clock generating file as per required for the project.-this is fpga spartan 3e based project file .the project is the game based on vga. this file contains 2,20,25,400Hz clock generating file as per required for the project.

利用FPGA实现硬件的VHLD语言的Manchester code。(Hardware implementation using FPGA VHLD language Manchester code.)

pid程序,新学者，使用FPGA学习，希望大家一起学习

verilog 编写的I2C程序，控制D/A的(I2C program written by Verilog to control D/A)

本文利用FPGA 可以弥补硬件插补器的不足，是执行速度提高，且可与运动控制部分很好的集成，制成运动控制器，实现高速运动控制

实现简单自动售货机的基本功能。投币找零功能，并用Led数码管显示，输出结果用Led显示。(Basic functions simple vending machines. Coin change for function and use Led digital tube display, the output display Led.)

JESD204协议简单透彻的讲解，对做高速AD的朋友有一定的帮助(Understanding control characters in JESD204)