135个经典VerilogHDL源码和说明文档，入门的好资料

verilog 代码实现串并转换，有延迟(Verilog code and string conversion, delay)

very nice program that i ensure anyone can use easily and will be efficient for hard project of elevator

verilog语言设计的VGA驱动。在Quarus11.0下编译成功，并在Altera cyclone4开发板上测试OK(verilog language design VGA driver. In Quartus11.0 successfully compiled and Altera cyclone4 development board test OK)

adc采集多路采集多通道基于dma的adc采集(ADC acquisition, multi-channel acquisition and multi-channel acquisition)

说明：  自己写的DES的verilog实现。输入输出实现了并转串。(DES algorithm implemented in verilog.)

原创，帧同步器的Verilog代码，在FPGA上验证实现过，无误。作为通信系统帧传输的仿真，有限状态机同步态和失步态的切换仿真。(Original Verilog code for frame synchronization, verify the implementation on the FPGA, and correct. Frame transmission as the communication system simulation, finite state machine synchronous state and the loss of the switching simulation of gait.)

VHDL语言，设计一个在DE2平台的8个七段数码管上循环显示HELL0的程序，采用按键控制循环的速度，慢速循环时间间隔为1S，快速循环时间间隔为200ms。(VHDL language, design a platform in the DE2 8 segment digital tube display HELL0 program cycle, the speed control loop using keys, slow cycle time interval for the 1S, fast cycle time interval is 200ms.)

that file is different I2S example

ov7620的CPLD采集程序，VHDL语言-ov7620 CPLD acquisition procedures, VHDL

3-8译码器实验，用三个拨码开关控制8个LED中某一个点亮