登录
首页 » VHDL » 内附多路选择器,74系列芯片VHDL源码,加法器,FIR,比较器等大量例子,对初学VHDL语言很有好处。可用maxplus,quartus,synplicity...

内附多路选择器,74系列芯片VHDL源码,加法器,FIR,比较器等大量例子,对初学VHDL语言很有好处。可用maxplus,quartus,synplicity...

于 2022-08-11 发布 文件大小:227.83 kB
0 210
下载积分: 2 下载次数: 1

代码说明:

内附多路选择器,74系列芯片VHDL源码,加法器,FIR,比较器等大量例子,对初学VHDL语言很有好处。可用maxplus,quartus,synplicity等综合软件进行调试-contains multiple-choice, 74 chips VHDL source code, the adder, FIR, comparators, etc. are plenty of examples for beginners VHDL very good. Available maxplus, Quartus, synplicity integrated software debugging

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • FFT
    使用VHDL语言实现对快速傅立叶变换算法的实现,并通过仿真验证其正确性。(Using VHDL language implementation for the realization of fast Fourier transform algorithm, and its correctness is validated by computer simulation.)
    2021-04-03 21:49:05下载
    积分:1
  • 1、 利用FLEX10的片内RAM资源,根据DDS原理,设计产生正弦信号的各功能模块和顶层原理图; 2、 利用实验板上的TLC7259转换器,将1中得到的正弦信...
    1、 利用FLEX10的片内RAM资源,根据DDS原理,设计产生正弦信号的各功能模块和顶层原理图; 2、 利用实验板上的TLC7259转换器,将1中得到的正弦信号,通过D/A转换,通过ME5534滤波后在示波器上观察; 3、 输出波形要求: 在输入时钟频率为16KHz时,输出正弦波分辨率达到1Hz; 在输入时钟频率为4MHz时,输出正弦波分辨率达到256Hz; 4、 通过RS232C通信,实现FPGA和PC机之间串行通信,从而实现用PC机改变频率控制字,实现对输出正弦波频率的控制。-a use FLEX10-chip RAM resources, in accordance with DDS principle, design sinusoidal signal generated by the top-level functional modules and schematics; 2, the experimental board TLC7259 converters, will be a sinusoidal signal, the D/A conversion, after filtering through the ME5534 oscilloscope observation; 3, the output waveform requirements : the input clock frequency of 16KHz, sine wave output resolution of 1Hz; the input clock frequency of 4MHz, the sine wave output resolution of 256Hz; 4, RS232C communications, FPGA and PC serial communications between in order to achieve PC-frequency control characters, the realization of sine wave output frequency control.
    2022-01-25 19:12:14下载
    积分:1
  • c51
    51数字钟带各种扩展年,月,日等并且可预置。用汇编语言写的(51 digital clock with extended assembly language)
    2012-11-09 08:41:02下载
    积分:1
  • fft
    说明:  用FPGA实现8点fft,整个代码使用verilog编写,主要运用了加法器和乘法器,简单易懂(8-point FFT with FPGA, The whole code is written by Verilog, mainly using adder and multiplier, which is easy to understand)
    2021-03-29 20:59:10下载
    积分:1
  • Based on quartus a 3
    基于quartus的3-8译码器,可作为大型系统的译码器模块-Based on quartus a 3-8 decoder can be used as large-scale system decoder module
    2022-03-14 15:00:50下载
    积分:1
  • hwref
    spartan 3 hardware reference document xilinx
    2009-05-22 19:10:33下载
    积分:1
  • vga_core
    Code VHDL for control VGA FPGA: Xilinx, Altera
    2012-09-09 10:54:28下载
    积分:1
  • pwm
    实现pwm波的输出,按键可调占空比的,可通过连接pwm输出值led灯以检测占空比的变化(To realize the output of the PWM wave, key adjustable duty ratio, but through the connection PWM output value led lamp with testing duty ratio changes )
    2020-12-20 21:19:08下载
    积分:1
  • EP2C70F896C6N-pins
    将VHDL程序下载到DE2开发板,引脚分配时需要知道的芯片每个引脚功能(VHDL program will be downloaded to the DE2 development board, you need to know when the pin assignments for each pin of the chip functions)
    2020-12-09 11:09:21下载
    积分:1
  • 本代码实现了全加器功能,适合初学者学习
    本代码实现了全加器的功能,可供初学者学习-This code implements a full adder functions, for beginners to learn
    2022-03-09 20:15:10下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载