内附多路选择器，74系列芯片VHDL源码，加法器，FIR，比较器等大量例子，对初学VHDL语言很有好处。可用maxplus，quartus，synplicity...

正弦波在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-sine wave in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim

4X4keypad的防抖动模块，用于假按键的检测-4X4keypad shake the module, the keys for false detection

基于用户自定义模块的实时时钟的设计；Qsys硬件设计；(Custom real-time clock module-based design Qsys hardware design )

《CPLDFPGA嵌入式应用开发技术白金手册》源代码，涉及FPGA/CPLD的各个方面，键盘扫描，LED扫描等简单程序及滤波器等的设计(" CPLDFPGA platinum embedded application development technology handbook" source code, related to FPGA/CPLD all aspects of the keyboard scanning, LED scanning filters, such as simple procedures and design)

Shift reg in vhdl, a first example to start

采用costas环进行DPSK解调的程序。输入数据速率2.4Kbps，载波频率12KHz，采样率1.6MHz， 输入数据位宽12位，快捕带为799.617Hz(Costas ring using DPSK demodulation process. Input data rate 2.4Kbps, carrier frequency 12KHz, sampling rate 1.6MHz, the input data 12 bits wide, fast catching band is 799.617Hz)

1024点fft verilog hdl-1024-point fft verilog hdl

基于FPGA 的12864液晶显示汉字，用verilog编写的。(12864 liquid crystal display Chinese characters based on FPGA, written in verilog.)

Am29LV160D数据基本知识手册，基本原理及工作方式。(Am29LV160D Data basic knowledge Manual, the basic principle and ways of working.)

这是一个HDB3编码器，可以将普通的二进制序列转化为符合HDB3编码规则的双极性序列-This is a HDB3 encoder, can be transformed into an ordinary binary sequences in order to comply with the rules of HDB3 bipolar coding sequence