登录
首页 » VHDL » 内附多路选择器,74系列芯片VHDL源码,加法器,FIR,比较器等大量例子,对初学VHDL语言很有好处。可用maxplus,quartus,synplicity...

内附多路选择器,74系列芯片VHDL源码,加法器,FIR,比较器等大量例子,对初学VHDL语言很有好处。可用maxplus,quartus,synplicity...

于 2022-08-11 发布 文件大小:227.83 kB
0 181
下载积分: 2 下载次数: 1

代码说明:

内附多路选择器,74系列芯片VHDL源码,加法器,FIR,比较器等大量例子,对初学VHDL语言很有好处。可用maxplus,quartus,synplicity等综合软件进行调试-contains multiple-choice, 74 chips VHDL source code, the adder, FIR, comparators, etc. are plenty of examples for beginners VHDL very good. Available maxplus, Quartus, synplicity integrated software debugging

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • PCIe
    本书共由三篇组成。其中第一篇由第1~3章组成,介绍PCI总线的基础知识。第二篇 由第4~13章组成,介绍PCIExpress总线的相关概念。第二篇的内容以第一篇为基础。(This book comprises a total of three components. The first chapter from the first 1-3 chapters, introduces the basics of the PCI bus. Second by the first 4 to 13 chapters, introduces concepts related PCIExpress bus. The contents of the first to second basis.)
    2020-06-26 17:20:02下载
    积分:1
  • VHDL实现SPI功能源代码
    VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.-SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the
    2022-01-26 00:50:40下载
    积分:1
  • reader
    实现verilog读写txt文件,从sut.txt从读取数据,进行操作后,写入out.txt(Realize verilog read and write txt file)
    2020-11-15 21:29:41下载
    积分:1
  • code
    涉及到常用的模块,参数可配置,可以很方便的集成到应用中(Related to commonly used modules, parameters can be configured, can be easily integrated into applications)
    2008-06-13 22:30:14下载
    积分:1
  • LVDS-application-Verilog-HDL-code
    LVDS的应用的Verilog HDL例子程序(LVDS example of the application procedures for the Verilog HDL)
    2011-09-30 20:24:02下载
    积分:1
  • I2CVHDLASDASDADASD
    内容太短。注意请: 代码没有很好的描述将被删除,你不会得到任何点。请描述一下更好地获得更多积分。
    2022-11-26 06:20:03下载
    积分:1
  • asynchronous serial communication port of the FPGA, function (1) serial data rec...
    异步串口通信口在FPGA实现,功能有(1)串行数据接收的同步控制;(2) 串行数据发送的同步控制-asynchronous serial communication port of the FPGA, function (1) serial data receiver synchronization control; (2) the transmission of serial data synchronization control
    2023-06-21 16:25:03下载
    积分:1
  • This tutorial presents an introduction to Altera’s Nios R II processor, which...
    This tutorial presents an introduction to Altera’s Nios R II processor, which is a soft processor that can be in- stantiated on an Altera FPGA device. It describes the basic architecture of Nios II and its instruction set. The NiosII processor and its associated memory and peripheral components are easily instantiated by using Altera’s SOPCBuilder in conjuction with the Quartus R II software.
    2023-06-21 11:25:02下载
    积分:1
  • det
    double edfe trigger d latch
    2014-01-07 19:55:29下载
    积分:1
  • 一组练习,关于VHDL的一些基础的知识和练习可以参考一些具体的问题...
    一组练习,关于VHDL的一些基础的知识和练习可以参考一些具体的问题-A group of exercises, on a number of VHDL-based knowledge and practice can refer to some specific questions
    2022-03-21 23:32:32下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载