登录
首页 » VHDL » 6. For the key to enter a password lock, assuming that reset after the seven lam...

6. For the key to enter a password lock, assuming that reset after the seven lam...

于 2022-03-11 发布 文件大小:663.40 kB
0 150
下载积分: 2 下载次数: 1

代码说明:

6对于进入密码锁的按键,假设复位后七个灯显示" 0",使用sw1、sw2 2,然后只要按下并松开sw2,七个灯上就显示" 2",而只要按下并松开sw1,七个灯上就正确显示值" 1

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • code
    代码文件夹: ARVI_FSM.v为顶层文件,用于模拟时用。 dataHex.dat 为模拟输入文件(只有10行,象征的意思。实际我们模拟时,dataHex.dat文件足有1个多GB) dataFormat.dat为输入文件对应的带格式的文件 使用modelsim模拟时,将dataHex.dat名字改为CPUContext.txt 结果: result.txt (Code folder: ARVI_FSM.v for top-level documents used for the simulation. dataHex.dat for analog input files (only 10 line, the meaning of the symbol. actual simulation we, dataHex.dat documents have more than one full GB) dataFormat.dat for the input file the corresponding file with modelsim simulation used to dataHex.dat name to CPUContext.txt results: result.txt)
    2009-06-21 19:14:37下载
    积分:1
  • eDP
    eDP接口TFT-LCD显示驱动原码(verilog+c)(eDP Interface TFT-LCD display driver source code (verilog+c))
    2020-10-17 09:17:27下载
    积分:1
  • VHDL实现简单的8位CPU doc文件上有源代码
    VHDL实现简单的8位CPU doc文件上有源代码-VHDL simple eight CPU doc documents Active code
    2023-01-26 05:05:03下载
    积分:1
  • FPGAAD9854DDS
    FPGA测序和DDS产生各种波形程序,用Atral器件开发(FPGA sequencing and DDS generate various waveform programs.)
    2018-11-14 22:07:21下载
    积分:1
  • fpga_dsp_simple
    dsp和fpag通信的测试程序,包含整个工程和signaltap测试信号。(the the dsp and fpag communications test procedures, including the entire the engineering and signaltap test signal.)
    2013-04-14 15:17:20下载
    积分:1
  • 通信协议AHB_LITE
    AHB_Lite 通信协议的FPGA Verilog 设计(AHB_Lite communication protocol Verilog design in FPGA)
    2020-12-15 10:09:14下载
    积分:1
  • 用Verilog做的SD卡控制器(有详细的注释)
    说明:  SDIO 接口,实现SD卡的控制器功能,带有详细的注释(SDIO Interface,to realize the controller of SD Card,and have detail description.)
    2020-06-16 22:00:01下载
    积分:1
  • DDS 基于FPGA的任意波形信号发生器
    基于FPGA的任意波形信号发生器,可实现频率、幅度、相位的调节,输出方波、正弦波、锯齿波(Arbitrary waveform generator based on FPGA)
    2017-05-22 15:54:24下载
    积分:1
  • 65位FIR数字滤波器的设计~~其中有通过仿真得出得数据 ~可以通过数据输入完成滤波实验~对数字滤波器得整个算法进行了分析包括输入分组相加 然后相乘得过程...
    65位FIR数字滤波器的设计~~其中有通过仿真得出得数据 ~可以通过数据输入完成滤波实验~对数字滤波器得整个算法进行了分析包括输入分组相加 然后相乘得过程-65 FIR digital filter design ~ ~ with simulation data to come in through the importation of data from experiments completed filtering of the digital filter in the whole algorithm analysis including input a sum then multiply in the process
    2022-01-30 18:45:51下载
    积分:1
  • Dec_mul
    时间同步后即可确定每帧数据的起始位置,这样就能完整的截取下每一帧。但是,数据中还带有频偏信息。在常规的通信系统中,多普勒很小仅仅会带来很小的频偏,但是在大多普勒的情况下,频偏将非常大,20马赫的速度将会带来将近34K的频偏。因此,如何很好的纠正频偏即为本系统的难点。 OFDM中,我们将大于子载波间隔倍数的频偏称为整数倍频偏,而将小于一个子载波间隔的频偏称为小数倍频偏。频偏矫正精度只要能保证小于十分之一倍的子载波间隔,频偏就不会对均衡和解调造成影响。本文中我们借鉴这种思想,由于硬件资源限制,我们将在接收端做64点FFT,即相当于将频域划分为64份,我们将小于 的频偏称为小数倍频偏,将 整数倍的频偏称为整数倍频偏。本程序即基于SCHIMDL经典方法完成小数倍频偏纠正(After time synchronization can determine the starting position of each frame data, so you can complete the interception of each frame. However, in the data with frequency information. In conventional communication systems, doppler small will bring only small deviation, but in the case of most of the doppler, frequency PianJiang is very large, 20 Mach speed will lead to deviation of nearly 34 k. Therefore, how to good to correct deviation is the difficulty of this system. OFDM, we will be bigger than the sub-carrier spacing ratio of frequency deviation is called the integer frequency offset, and the interval will be less than a child carrier frequency offset is called decimal frequency doubling. Deviation is less than one over ten times as long as can guarantee accuracy of sub-carrier spacing, deviation will not affect balance and demodulation. This article, we draw lessons from the idea, due to the limited hardware resources, we will do 64 points FFT at the receiving end, which is equ)
    2013-12-26 18:00:24下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载