6. For the key to enter a password lock, assuming that reset after the seven lam...

说明：  RISC全部源码，包含仿真文件，使用makefile脚本编写，能通过vcs编译(RISC all source code, including simulation files, using makefile script, can be compiled through VCS)

FPGA数字AGC(帮同学做的毕业设计)-FPGA digital AGC (help students to do the graduation project)

SAP-1硬件描述语言（使用Verilog语言）

基于VHDL的LCD显示程序,包含完整的源代码,锁脚文件以及下载文件,可直接下载使用-VHDL based on the LCD display program, including complete source code, locking pin, as well as download files documents can be directly downloaded using

一个简单的FM调制模块，FM发射，用Verilog编写，基于Xilinx SPARTAN6 XC6LX9开发(A simple FM modulation modules for FM transmitter, using Verilog prepared, based on XILINX SPARTAN6 XC6LX9 Development)

用verilog实现对三个16位数进行相加乘法器(Three 16-digit sum of the multiplier Verilog)

I2C总线控制器 altera提供的VHDL的源程序代码-I2C Bus Controller ALTERA the VHDL source code

华为内部资料，华为FPGA全套资料，包括华为的专利设计(Internal information Huawei Huawei FPGA complete information, including Huawei' s patented design)

8位相等比较器，比较8位数是否相等 -- 8-bit Identity Comparator -- uses 1993 std VHDL -- download from www.pld.com.cn & www.fpga.com.cn-eight other phase comparators, Comparing the same whether the median 8-- 8-bit Identity Comparator-- uses 1993 std VHDL-- download from www.pld.com.cn

说明：  此程序用来实现图像的采集和帧数的计算功能。(Image acquisition and calculation of the number of frames.)