6. For the key to enter a password lock, assuming that reset after the seven lam...

数字计时器，使用VHDL语言编写，使用数码管显示，精确到ms-digital timer, the use of VHDL development, the use of digital control, the precision of the ms

用verilog写的，基于查表法实现的LOG10运算器，在Altera FPGA中应用。-It is a verilog design of LOG10 calculation unit, which is based on LUT arithmatic. And it is applicated in Altera FPGA.

控制步进电机转动，正反转，旋转角度完美掌握。很好用，亲测(Control stepping motor rotation, positive and negative rotation, perfect control of rotation angle. Very easy to use, personal test)

Spartan-3E板卡XC2C64A CPLD 的代码(the XC2C64A CPLD on the Spartan-3E Starter Kit boards)

--author: Suntion Tang --date: 2008-6-7 -- two warning --modify: By Suntion Tang at 2008-6-14 --description: 顶层文件，由于此系统简单， -- 且底层文件不多，故放弃原理图描述，采用VHDL语言描述-author: Suntion Tang date: 2008-6-7 two warning modify: By Suntion Tang at 2008-6-14 description: the top-level documents, as a result of this system is simple, and not more than the bottom of a document, they give up the schematic description of the use of VHDL language description

crc校验,经验证正确,下载就可直接用,有不足的地方可以指正,-CRC check, certified correct, you can download directly, there are deficiencies can correct me,

说明：  模拟交通灯 verilog CPLD EPM1270 源代码(Simulation of traffic lights verilog CPLDEPM1270 source code)

串口程序，基于VHDL 的，很好的程序 快下吧-Serial procedures, based on VHDL, and a very good program, are you fast

说明：  实现AXI,AXI-Lite乒乓地址的传输，AXI,AXI-Lite已经封装成内核，可直接修改后使用(Realize the transmission of table tennis address of Axi and Axi Lite. Axi and Axi Lite have been encapsulated into a kernel, which can be directly modified and used)

说明：  demo6 蜂鸣器实验 蜂鸣器演奏音乐(demo6 buzzer buzzer experiment playing music)