dp_xiliux the CPLD Verilog design experiments, serial presentation. code test.

Verilog HDL的PLI子程序接口，用于与用户C程序在2个方向上传输数据，可用xilinx ISE，quartusii或modelsim仿真，-Verilog HDL PLI subroutine interfaces, for C program with the user in the direction of two transmission of data, available xilinx ISE. quartusii or modelsim simulation,

verilog实现的奇数分频器 针对任何规模的奇数分频-verilog prescaler for the realization of the odd-numbered odd-numbered points of any size-frequency

给出了SVPWM算法的详细FPGA实现方法！(A detailed FPGA SVPWM algorithm to achieve the method!)

vhdl描述的显示代码 maxplus2开发环境-VHDL description of the display code development environment maxplus2

xilinx公司的FPGA实现数字视频信号处理器。语言是VHDL。-Xilinx FPGA to achieve the company

说明：  阿尔泰PCI8664的采集卡labview程序(PCI8664，labview，programm)

altear max10 adc demo，实验使用了2个adc，最大支持18路adc(altear max 10 demo with 2 adc， max support 18 channel adc)

设计一简易数字频率计，其基本要求是： 1)测量频率范围0～999999Hz； 2)最大读数999999HZ,闸门信号的采样时间为1s；. 3)被测信号可以是正弦波、三角波和方波； 4)显示方式为6位十进制数显示； 5）具有超过量程报警功能。 5)输入信号最大幅值可扩展。 6）测量误差小于+-0.1%。 7)完成全部设计后，可使用EWB进行仿真，检测试验设计电路的正确性。(The basic requirements of designing a simple digital frequency meter are: 1) The measuring frequency range is 0-999999 Hz. 2) The maximum reading is 999999HZ, and the sampling time of gate signal is 1 s. 3) The measured signal can be sine wave, triangle wave and square wave. 4) The display mode is 6-bit decimal number display. 5) It has alarm function beyond range. 5) The maximum amplitude of input signal can be expanded. 6) The measurement error is less than +0.1%. 7) After completing all the design, EWB can be used to simulate and test the correctness of the circuit.)

很不错的资源哦，这是我在实验室当年总结的关于nios timer的程序段(nios timer)

基于Verilog的八层电梯设计，能够实现自动化的电梯控制。-Verilog based on the eight-lift designed to automate the elevator control.