dp_xiliux the CPLD Verilog design experiments, serial presentation. code test.

This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM. The core acts as a slave WISHBONE device. The output is perfectly compatible with any sound player with the IMA ADPCM codec (included by default in every Windows). Includes a testbench that takes an uncompressed PCM 16 bits Mono WAV file and outputs an IMA ADPCM compressed WAV file. Compression ratio is fixed for IMA-ADPCM, being 4:1. PLEASE NOTICE THAT THIS CORE IS LICENSED UNDER http://creativecommons.org/licenses/by-nc-sa/3.0/ (Creative Commons Attribution-Noncommercial-Share Alike 3.0 Unported). That means you may use it only for NON-COMMERCIAL purposes.

Commponent for drivering EEPROM memory AT25320 from Avalon bus.

一种能简单的实现I2C通讯的代码，对于主机和从机之间的通讯讲解的很清楚。(A Code for I2C Communication)

基于cycloneIIFPGA芯片Ep2c5t144c8的解调程序，用VHDL语言生成-CycloneIIFPGA chip-based demodulation Ep2c5t144c8 procedures, using VHDL language generation

master spi的源代码（verilog），包括文档，测试程序(master spi the source code (verilog), including documentation, testing procedures)

《Verilog HDL 程序设计教程》4-"Verilog HDL Design Guide" 4

is61lv25616简单的verilog程序，完成sram读写(is61lv25616 simple verilog program, complete sram read and write)

Verilog_HDL源码 -Verilog_HDL source Verilog_HD L FOSS Verilog_HDL FO

通过代码控制音频编/解码硬件芯片WM8731， 通过按键控制音频输出的音量(Audio codec hardware chip WM8731 is controlled by code, and audio output volume is controlled by keys.)

ISE时序约束笔记——Global Timing Constraints，这个文档中详细介绍了如何使用ISE中约束工具和原理，对fpga水平提高有很大帮助(In this file , global timing constraints is introduced very clearly. It can really helps)