xilinx公司的FPGA实现数字视频信号处理器。语言是VHDL。

基于单片机和FPGA实现DPSK调制解调的功能和分类比较。(MCU and FPGA implementation based on DPSK modulation and demodulation functions and classification comparison.)

三八译码器，四位加法器，EDA实验，用verilog编写(EDA experiment with verilog language)

verilog语法说明，包含verilog golden reference guide，verilog 2001语法(verilog golden reference guide)

The deep lecture notes for basic digital system for cmos design

verilog写的数字频率计的显示模块,可以-written in Verilog Digital Cymometer display module can be

此是进行循环冗余效验的Verilog编码，适合多种标准，如CRC16(this Cyclic Redundancy is well-tested Verilog code for a variety of criteria, such as CYXLIC REDUNDANCY)

一个用VerilogHDL语言编写的多路解复用器-a Verilog HDL language used in the preparation of multi-channel demultiplexer

基于FPGA的JPEG解码，对开发图片解码的人有用。(FPGA-based JPEG decoding, the development of image decoding useful.)

摘 要：以上海地区的出租车计费器为例，利用Verilog HDL语言设计了出租车计费器，使其具有时间 显示、计费以及模拟出租车启动、停止、复位等功能，并设置了动态扫描电路显示车费和对应时间，显示 了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。源程序经MAX+PLUS Ⅱ软件调试、优 化，下载到EPF1OK10TC144—3芯片中，可应用于实际的出租车收费系统。 关键词：Verilog HDL；电子自动化设计；硬件描述语言；MAX+PLUSⅡ(Abstract: Shanghai taxi meter as an example, the use of Verilog HDL language designed taxi meter so that it will have the time display, billing, as well as analog taxis to start, stop, reset and other functions, and set up a dynamic scanning circuit shows that the fare and the corresponding time, shows the hardware description language Verilog-HDL design of the superiority of digital logic circuits. Source by MAX+ PLUS Ⅱ software debugging, optimization, downloaded to EPF1OK10TC144-3 chip, can be applied to the actual taxi fare collection system. Keywords: Verilog HDL electronic design automation hardware description language MAX+ PLUS Ⅱ)

频率计，ＶＥＲＩＬＯＧ代码，含详细　中文注释．-Cymometer, VERILOG code, containing a detailed Chinese Notes.