xilinx公司的FPGA实现数字视频信号处理器。语言是VHDL。

利用quartus II 软件采用verilog语言设计了一个sigmoid激活函数(this work is a sigmoid ,use verilog language)

页面置换算法中的三种算法相关程序代码 FIFO LUR OPT-yemianzhihuansuanfa

s5pv-u-boot-2011.06之增加LCD显示功能(s5pv-u-boot-2011.06 Increase LCD display function)

ep2c5 实现 定时器 verilog语言，quartus 2 仿真-verilog language to achieve ep2c5 timer, quartus 2 Simulation

基于XIlinx ISE，用Verilog语言实现3分频电路，适合初学者(Based XIlinx ISE, Verilog language using the frequency dividing circuit 3, suitable for beginners)

假设每个从设备中有可访问APB寄存器16个，位宽均为32比特，16个寄存器的访问地址计算方式为 基址 +　寄存器编号左移２位（byte 偏移）(Assuming that there are 16 accessible APB registers in each slave device, the bit width is 32 bits, and the access address of 16 registers is calculated by base address + register number left shift 2 bits (byte offset).)

nios大神进阶，一本非常好的FPGA书籍，从RTL到eclips(nios tech.a very good book learning FPGA tech.)

Altera board Mp3 project

FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation

xilinx verilog FPGA驱动AD9613 数据采集DEMO程序(Xilinx Verilog FPGA drives AD9613 data acquisition DEMO program.)