频率计，vhdl语言， ispDesignEXPERT

主要编写了一组二进制数据通过根升余弦滤波器后的波形，但并没有使用ISE内部的FIR滤波器内核，该程序相当于编写了一个根升余弦滤波器。(Mainly prepared a set of binary data through the root raised cosine filter waveform after, but did not use the ISE internal FIR filter kernel, the program is equivalent to the preparation of a root raised cosine filter.)

数字频率计的设计，显示0~999的频率 整个程序代码都是通过vhdl语言来完善的 功能模块多样，详细的介绍了多模块的各个功能

This a verilog file which is used as a decoder-This is a verilog file which is used as a decoder

高速多通道crc实现，可以并行实现5个通道数据的校验，支持10GB以太网标准-High-speed multi-channel crc implementation, can be achieved in parallel 5-channel data validation, support for 10GB Ethernet standard

使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上用硬件描述语言实现一个ROM存储器。-The use of Altera" s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 development board with hardware description language to achieve a ROM memory.

programe reverse a string in c

this ebook for electronics hobbiest. VHDL for Beginners

mico8  vhdl  project lattice出的小资源mcu 256luts  值得学习

A quick and simple Spartan 3 tutorial

verilog 写的 电话计费器程序-verilog to write a telephone billing program