频率计，vhdl语言， ispDesignEXPERT

利用verilog HDL逐点比较法实现直线和圆弧插补(Use verilog HDL by-point comparison method to achieve linear and circular interpolation)

SDIO slave verilog code

VCS详细学习资料。内涵专业研究院所内部培训资料。适合于初学者学习使用，易于上手。(VCS learning)

FPGA-CPLD实习计数器7段数码管控制接口设计与LED显示控制，FPGA译码(FPGA-CPLD internship counter 7-segment LED control interface design and LED display control, FPGA decoder)

实现的电子钟，资料非常全面，是一次课程设计的大作业，完成的质量很高。(Achieve the electronic clock information is very comprehensive, curriculum design job, completed high quality.)

vhdl子程序，本人收集的，比较常用的代码-VHDL subprogram, I collected to compare commonly used code

8位十六进制频率计设计 根据频率的定义和频率测量的基本原理，测定信号的频率必须有一个脉宽为1s的输入信号脉冲计数允许信号；1s计数结束后，计数值被锁入锁存器，计数器清零，为下一测频计数周期做好准备。测频控制信号可由一个独立的发生器（FTCTRL）来产生。-8-bit hexadecimal Cymometer designed in accordance with the definition of frequency and frequency of the basic principles of measurement to determine the frequency of the signal must have a pulse width of the input signal for 1s permit pulse counting signal 1s counting after the total value was locked into the lock depositors, counters cleared for the next count cycle frequency measurement ready. Frequency control signal generator may be an independent (FTCTRL) to generate.

密码锁 vhdl实现的密码锁 控制程序-mimasuo

例如分频器，alu，ram的verilog实现(The implementation of divider, alu, ram etc. in verilog)

4*4键盘设计，能运行，是我自己编译的，是初学者的工具(4* 4 keyboard design, can run my own compilation, is a tool for beginners)