频率计，vhdl语言， ispDesignEXPERT

Xilinx公司网站下的SDRAM Controller的参考设计，经过验证-Xilinx website of SDRAM Controller reference design, validated

FPGA VERILOG 用DCFIFO实现 跨时钟域的数据传输，已验证，直接可用-FPGA VERILOG using DCFIFO realize cross-clock domain data transfer, has been verified, directly available

基于PID 控制算法的直流电机控制，输出PWM波，很容易用(motor control)

  基于FPGA(Field-Programmable Gate Array)的OFDM(Orthogonal Frequency Division Multiplexing)信号传输系统VHDL源码 use IEEE.std_logic_unsigned.all; package outconverter is constant stage : natural := 3; constant FFTDELAY:integer:=13+2*STAGE; constant FACTORDELAY:integer:=6; constant OUTDELAY:integer:=9; function counter2addr( counter : std_logic_vector; mask1:std_logic_vector; mask2:std_logic_vector ) return std_logic_vector; function outcounter2addr(counter : std_logic_vector) return std_logic_vector; end outconverter; package body outconverter is function counter2addr( counter : std_logic_vector; mask1:std_logic_vector; mask2:std_logic_vector ) return std_logic_vector is variable result :std_logic_vector(counter"range); begin for n in mask1"range loop if mask1(n)="1" then result( 2*n+1 downto 2*n ):=counter( 1 downto 0 ); elsif mask2(n)="1" and n/=STAGE-1

A Dec example written in VHDL.

4*4键盘设计，能运行，是我自己编译的，是初学者的工具(4* 4 keyboard design, can run my own compilation, is a tool for beginners)

verilog code for 3 bit sequence detector

VHDL数字系统设计和工程实践1，包含原理，真值表和原理图，以及VHDL源代码.-VHDL digital system design and engineering practice, one that contains principles, truth table and schematic, as well as VHDL source code.

这是一个LCD1602底层驱动代码，TI公司LM3S系列的(This is a LCD1602 underlying driver code, TI company LM3S series)

华为内部资料，华为FPGA全套资料，包括华为的专利设计(Internal information Huawei Huawei FPGA complete information, including Huawei' s patented design)