频率计，vhdl语言， ispDesignEXPERT

说明：  designers guide to vhdl(third edition)这本书好像在国外vhdl入门中挺流行的, 爱思维尔有资源,但是是各个章节散装的, 我把它们合成了(The book designers guide to vhdl (third edition) seems to be very popular in foreign vhdl entry. Ixel has resources, but it is a loose chapter of each chapter, I synthesized them)

32bits FIFO with synchronizer. pass the synthesis using Synopsys tools-bits FIFO with synchronizer. Pass the sy nthesis using Synopsys tools

线性伸展TDC的verilog，包含门级网表(TDC linear stretch of verilog, includes gate-level netlist)

VHDL语言的cookbook,能够使你更快的学会使用VHdL-cookbook

double edfe trigger d latch

nios学习资料，fpga调用外部sdram实例，值得初学者下载。(nios learning materials, fpga call external sdram instance, it is worth beginners to download.)

verilog code for 3 bit sequence detector

周立功Verilog HDL黄金参考指南，学习VerriLog的东西。-Golden Week Ligong Verilog HDL reference guide, learning VerriLog things.

一个实用的uart协议模块，使用verilog 实现(A practical uart protocol modules, use verilog to achieve)

说明：  多路信号复用基带系统的建模与设计,按位同步复接并掌握四路同步复接器的VHDL设计及系统的时序仿真。(library ieee use ieee.std_logic_1164.all use ieee.std_logic_unsigned.all )