Verilog代码为3位序列检测器

source vhdl code of D flipflop logic

用Verilog语言实现的FPGA UART独立收发模块 思路简单，代码简洁。在Lattice LFE3EA VERSA开发板上验证通过,编译器Lattice Diamond. 功能：串口收到数据后立即回传，此后每一秒串口数据+1再发送。(Using Verilog language independent of FPGA UART transceiver idea is simple, concise code. Development board in Lattice LFE3EA VERSA verified by the compiler Lattice Diamond. Features: Serial data is received immediately after the return, then every second serial port and then send the data+ 1.)

七段数码管显示数字时 使用VHDL语言编写(VHDL The seven-segment LED display digital clock)

LTE上行链路使用的DFT-S-OFDM系统的仿真，其中包括QPSK星座映射、串并转换、N点DFT、子载波映射等。(LTE uplink using the DFT-S-OFDM system simulation, including QPSK constellation mapping, string and conversion, N-point DFT, subcarrier mapping, etc..)

用VHDL语言仿真音乐设计 用VHDL语言仿真音乐设计-Simulation using VHDL language music design music design simulation VHDL language

MAX2 EPLD 的测试程序, VHDL语言编写.-MAX2 EPLD testing code, VHDL language.

说明：  FPGA控制外边led，并实现跑马灯等多种效果，用户可以自行控制(FPGA control outside led)

VHDL examples for counter design, use QuickLogic eclips

Endat slave interface

用VHDL语言写的VGA 控制程序，已经验证过，绝对好用！-VHDL language used to write the VGA control procedures have been verified, the absolute ease of use!