Golden Week Ligong Verilog HDL reference guide, learning VerriLog things.

设计一简易数字频率计，其基本要求是： 1)测量频率范围0～999999Hz； 2)最大读数999999HZ,闸门信号的采样时间为1s；. 3)被测信号可以是正弦波、三角波和方波； 4)显示方式为6位十进制数显示； 5）具有超过量程报警功能。 5)输入信号最大幅值可扩展。 6）测量误差小于+-0.1%。 7)完成全部设计后，可使用EWB进行仿真，检测试验设计电路的正确性。(The basic requirements of designing a simple digital frequency meter are: 1) The measuring frequency range is 0-999999 Hz. 2) The maximum reading is 999999HZ, and the sampling time of gate signal is 1 s. 3) The measured signal can be sine wave, triangle wave and square wave. 4) The display mode is 6-bit decimal number display. 5) It has alarm function beyond range. 5) The maximum amplitude of input signal can be expanded. 6) The measurement error is less than +0.1%. 7) After completing all the design, EWB can be used to simulate and test the correctness of the circuit.)

说明：  URISC的RTL级设计，Verilog代码(Design: URISC RTL Verilog)

可编程逻辑器件cpld与单片机双向通信的源程序-Programmable logic device CPLD and MCU for two-way communication of the source

1 前大灯可以随意打开和关闭； 2 当汽车左转弯的时候，前左转向灯闪烁，同时左后灯的3盏灯由右往左闪烁； 3 当汽车有转弯的时候，前右转向灯闪烁，同时右后灯的3盏灯有左往右闪烁； 4 当汽车减速或紧急刹车的时候，左后灯和右后等同时闪烁； 5 当汽车在左转弯的同时减速，则前左转向灯闪烁，左后灯的3盏灯由右往左闪烁，同时右后灯都点亮。 6 当汽车在左转弯的同时减速，则前右转向灯闪烁，右后灯的3盏灯有左往右闪烁，同时左后灯都点亮。 -a former headlamps can be opened and closed at will; 2 when the vehicle made a left turn when the former left to lights flickered. Left lights while the three lights flashing from right-go left; 3 when the vehicle is making a turn when a right turn to the former lights flickered. Right after the lights while the three lights are blinking right and left; 4 when the vehicle deceleration or when the emergency brake, Left and right after the lights blink, and so on; 5 when the vehicle made a left turn at the same time to slow down, and then to the left before the lights flickered. Left lights three lights flashing from right-go left, right after the lights are lit. 6 when a car made a left turn at the same time to slow down, and then right before the lights to flick

说明：  VHDL语言写的SRAM控制程序，在开发板上验证过。(Written in VHDL SRAM control procedures, the development board verified.)

人的移动的跟踪，VERILOG实现，能跟踪人的画面移动(Tracking the movement of people, VERILOG realize that can track the person)

利用FPGA实现与powerpc的localbus数据接口代码。用verilog实现(localbus interface with PowerPC using Verilog)

WCDMA数字直放站中数字预失真研究及其FPGA实现(WCDMA Digital Repeater digital pre-distortion and its FPGA implementation)

SDRAM的驱动程序，主要是对SDRAM各类状态进行驱动，有刷新模块、读、写模块等。(The driver of SDRAM mainly drives various states of SDRAM, including refresh module, read and write module.)

本人初学VHDL时编的比较系统的VHDL源程序 巨实用 -I am learning more systematic series of practical VHDL source Giant