Golden Week Ligong Verilog HDL reference guide, learning VerriLog things.

说明：  FPGA锁相环实验： 顶层文件加底层IP文件构成 top中例化ip核pll(Experiment of Phase-Locked Loop Based on FPGA)

电梯的vhdl设计，6层楼含开关门，警报，内部请求，外部请求-Vhdl elevator design, six floors with switch doors, alarm, internal requests and external requests

adder_array的设计。加法器阵列设计，顶层模块，四步流水，21位(adder_array the design. The adder array design, top-level module, four-step pipeline, 21)

this program does something im not sure what but all i want is to get into the damn site thank you

VGA显示彩条DE2_70开发板 验证过的(VGA display color bar DE2_70 development board validated)

vhdl learnig material............

采用VHDL编写的步进电机控制程序-stepping motor controlling program written by VHDL

说明：  假设每个从设备中有可访问APB寄存器16个，位宽均为32比特，16个寄存器的访问地址计算方式为 基址 +　寄存器编号左移２位（byte 偏移）(Assuming that there are 16 accessible APB registers in each slave device, the bit width is 32 bits, and the access address of 16 registers is calculated by base address + register number left shift 2 bits (byte offset).)

自己写的 AXI master code(AXI master code)

LCD12864的显示程序，使用的是verilog语言编写的显示程序，为PDF文档(LCD12864 display program, using Verilog language display program, as a PDF document)