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ISE7.1,采用VIRTEX
ISE7.1,采用VIRTEX-II芯片。实现adc数据采样,平均,通道选择,采样时钟选择,数据格式调整,内含fifo,uart等模块。-ISE7.1, using VIRTEX-II chip. Adc realize data sampling, on average, channel selection, the sampling clock select, adjust data formats, including fifo, uart modules.
- 2022-03-28 19:34:46下载
- 积分:1
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能够实现8位的无符号数的乘除法,模拟了笔算的过程
- 2022-12-11 10:00:03下载
- 积分:1
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HDMI接口编解码传输模块ASIC设计_刘文杰
? 熟悉IIC协议总线协议,采用IIC总线对图像采集传感器寄存器进行配置,并转换为RGB565格式。
? 利用异步FIFO完成从摄像头输出端到SDRAM 和SDRAM 到VGA 接口各跨时钟域信号的传输和处理。
? 利用 SDRAM 接口模块的设计,实现了刷新、读写等操作;为提高SDRAM 的读写带宽,均采用突发连续读写数据方式;并采用乒乓操作实现 CMOS 摄像头与VGA的帧率匹配。
? 利用双线性插值方法实现对图像640×480到1024×768的放大操作。
? 完成VGA显示接口设计。(Familiar with IIC protocol bus protocol, IIC bus is used to configure the register of image acquisition sensor and convert it into RGB565 format.
Asynchronous FIFO is used to transmit and process signals across clock domain from camera output to SDRAM and SDRAM to VGA interface.
With the design of SDRAM interface module, refresh, read and write operations are realized. In order to improve the read and write bandwidth of SDRAM, burst continuous read and write data mode is adopted, and table tennis operation is used to achieve frame rate matching between CMOS camera and VGA.
The bilinear interpolation method is used to enlarge the image from 640*480 to 1024*768.
Complete the VGA display interface design.)
- 2020-06-25 04:00:02下载
- 积分:1
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Altera company s FPGA using VHDL to the development, use quartus2 9.0 software E...
使用altera公司的FPGA进行VHDL开发,使用quartus2 9.0 软件在EP1C3T144C8开发板上实现跑马灯输出。-Altera company s FPGA using VHDL to the development, use quartus2 9.0 software EP1C3T144C8 Development Board to achieve ticker output.
- 2022-02-02 20:51:33下载
- 积分:1
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Marquee procedures described in VHDL, for beginners to practice
VHDL描述的跑马灯程序,用于初学者练习-Marquee procedures described in VHDL, for beginners to practice
- 2022-05-27 22:24:01下载
- 积分:1
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135个经典VerilogHDL源码和说明文档,入门的好资料
135个经典VerilogHDL源码和说明文档,入门的好资料-135 Classic VerilogHDL source and documentation, a good data entry
- 2022-01-20 23:10:53下载
- 积分:1
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the_last
VHDL语言实现两个人掷骰子游戏,最多6次,大者胜则结束游戏并在点阵上显示,一直平手则一直进行直到达到6次。(Achieving the dice game between two people by using VHDL language.The maximum number of times is 6.The game will over when there is a biger one in one time,otherwise,the game will continue until the time of the game is up to 6.)
- 2021-01-21 12:18:42下载
- 积分:1
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rc6_decryption
rc6 algorithm designed based on verilog and is verified
- 2020-12-01 21:59:28下载
- 积分:1
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一个在FPGA芯片上实现UART功能的vhdl源代码,提供了UART的集成
一个在FPGA芯片上实现UART功能的vhdl源代码,提供了UART的集成-an FPGA chip to achieve UART function vhdl source code, providing integrated UART
- 2022-01-21 03:04:04下载
- 积分:1
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irdecode
自己编写的红外解码子程序,但CPU资源占用较高,作教学示范用途。(prepared their infrared decoding routines, but higher occupancy CPU resources for teaching demonstration purposes.)
- 2006-11-05 13:51:28下载
- 积分:1