bits FIFO with synchronizer. Pass the sy nthesis using Synopsys tools

verilog实现的基带信号编码，整个系统分为六个模块，分别为：时钟模块,待发射模块,卷积模块,扩频模块,极性变换和内插模块,成型滤波器(verilog implementation baseband signal coding, the entire system is divided into six modules, namely: the clock module, to be launched modules, convolution module, spread spectrum modules, polarity transform and interpolation modules, forming filter)

verilog 写的工程，是个基于流水线的乘法器(verilog write the works, is based on a pipelined multiplier)

在spartan－3e上利用八个led实现流水灯效果-Spartan-3e in the use of eight led lights to achieve the effect of flowing water

并行读写14路串口数据，数据被写入FIFO，在收到读写信号后，SPI发送数据出去(Parallel read and write 14 serial port data, SPI send data)

说明：  verilog编写的RS485读写驱动程序(RS485 read-write driver written by Verilog)

 本程序应用VHDL硬件描述语言，以QuartusⅡ8.0为开发工具设计了一个具有自动演奏乐曲功能的系统，演奏乐曲为《梁祝》，具有单曲播放器功能。本程序简单易懂，可作为FPGA入门学习之用。

自适应滤波，对输入信号进行选择性的加权处理，使输出达到最优化，并且能够跟踪和适应系统和环境的动态变化(Least mean square，of the input signal processing, selective weighted output, and optimize can track and adapt to the dynamic changes of the system and environment)

非常好的EPM570(CPLD)学习程序源码,适合初学者,能让其快速入门(Very good EPM570 (CPLD) learning program source code, suitable for beginners, allowing its Quick Start)

任意数据发生器的源代码-arbitrary data source code generator

PCI IP 核 Xilinx原版，很好用，国际知名公司Xilinx原版，值得信赖