bits FIFO with synchronizer. Pass the sy nthesis using Synopsys tools

用VHDL实现了希尔伯特滤波器,即就是幅度不变，而相位移动90度(use vhdl to accomplish the hilbert filter)

说明：  用于实现FPGA硬件开发使用的加法器，需要注意的是用Verilog语言实现的(The adder used to realize FPGA hardware development needs to be realized in Verilog language)

基于Montgoery 算法的RSA,FPGA verilog 实现，有测试文件(Based on Montgoery algorithm for RSA,FPGA verilog implementation，bench file)

Actel双端口存储；通过串口发送数据初始化RAM，然后通过串口返回到上位机的串口调试程序显示(通过串口发送数据初始化RAM，然后通过串口返回到上位机的串口调试程序显示)

说明：  基于BP算法的LDPC译码程序，采用vhdl语言，bp算法(BP algorithm based on LDPC decoding program using vhdl language, bp algorithm)

使用ISE软件实现OFDM通信系统的框架搭建，完成上板前的仿真工作(Realization of OFDM communication system with ISE software)

VGA controller : Genarate a VGA signal from your inout information as color info of each pixel

USB IPcoreIP核 包含文档(带说明)-USB IPcoreIP core includes a document (with instructions)

FPGA下PWM的Verilog 源码，含目标程序，可直接下载使用，可用在电机控制中-FPGA in Verilog source code under the PWM, including the target program, can be directly downloaded to use, can be used in motor control in

实现了四bit计数器的功能，使用的是VHDL语言描述(Four-bit counter, using the VHDL language description)