bits FIFO with synchronizer. Pass the sy nthesis using Synopsys tools

HDL example source code 1/5 dff_as

使用verilog hdl语言编程正弦波信号，能仿真出结果(Can use verilog HDL language programming sine wave signal, the simulation results )

用于实现上位机与下位机之间通过RS232协议来进行通讯。(It is used to realize communication between upper computer and lower computer through RS232 protocol.)

说明：  xilinx 平台的SPI从接口实现源码，供参考学习(used xilinx,slave-spi interface.)

VHDL编写的数字钟，在Q-ii下编译，实现闹铃设置与定时闹铃，分时秒显示-VHDL prepared digital clock, in the Q-ii under the compiler to achieve regular alarm and alarm settings, time-seconds display

用modelsim仿真一个正弦波产生程序-modelsim simulation using a sine wave generated procedures

说明：  华为 Verilog基本电路设计指导书--本文列举了大量的基本电路的Verilog HDL 代码，使初学者能够迅速熟悉基本的HDL 建模；同时也列举了一些常用电路的代码(Huawei Verilog basic circuit design instruction)

基于FPGA的键盘PS第二类编码方式的verilog解码程序。基于FPGA的键盘PS第二类编码方式的verilog解码程序。(FPGA keyboard PS encoding the verilog decoding procedures. FPGA keyboard PS encoding the verilog decoding procedures.)

Verilog，编写的udp收发程序，开发环境xilinx(Verilog, written UDP transceiver)

rc6 algorithm designed based on verilog and is verified