这是一个HDB3的译码器，实现从HDB3双极性码到高低电平二值序列的转化...

Lab view using FPGA traing on lcd pannel

说明：  risc 8 by coonan compatible with PIC16C57

Verilog-RISC CPU

用vhdl语言编写的基于FPGA的波形发生器。对于做实验需要产生的波形非常有用。-VHDL language using FPGA-based waveform generator. Does the need for experimental waveforms generated very useful.

本文介绍一种波导双模双带滤波器的设计方法。(This paper presents a new class of dual-mode dualband filters in which each polarization is dedicated to a selected band. The equivalent circuit is a parallel combination of two inline networks that represent each polarization. A transmission zero is generated between the two bands by properly adjusting the relative orientations of the input and output coupling apertures.)

ALTERA发布的内部FIFO读写示例，很有参考价值，对初学者会有一定的帮助(ALTERA' s internal FIFO read and write examples of great reference value, there will be some help for beginners)

说明：  使用Verilog，以Quartus II 为平台，编写了一个DDS信号发生器程序。(Using Verilog and Quartus II as the platform, realizing the DDS signal generator program .)

WOLA polyphase filter加权跌接累加FFT信道化技术(WOLA polyphase filter bank)

用于fpga学习，共同分享学习经验和交流学习心得-For fpga to learn, to share learning experiences and the exchange of learning

用FPGA实现数字锁相环，开发环境为ISE(Using FPGA digital phase-locked loop, development environment for ISE)