FPGA时钟闹钟+电子琴+lcd显示

VerilogHDL教程，很详细全面的Verilog教程，循序渐进，由浅入深，十分好的学习资料(VerilogHDL tutorial, very detailed and comprehensive Verilog tutorial, step by step, progressive approach, a very good learning materials)

多功能卡的源代码，verilog编写，用于多功能的数据接收-verilog code of mutiple function card

锡林克斯巴达官方文件有详细说明，支持斯巴达、顶点

Altera Sdram IP 源码，VHDL写的-Altera Sdram IP source code, VHDL written

verilog HDL编写的出租车计费系统-verilog HDL prepared Taxi Accounting System

这是一个在Quartus II软件中编写的vhdl程序。程序下载后可用蜂鸣器播放音乐 -This is a Quartus II software in the preparation of the VHDL program. After the buzzer can be used to download music player

给大家上传一本非常好的关于verilog-hdl的电子书，实用，易懂，易学。此为第七章(Give us a very good upload on verilog-hdl of e-books, practical, easy-to-understand, easy to learn. This is the Chapter VII)

USB2.0的VHDL描述，很经典了，欢迎大家下载-USB2.0 the VHDL description, very classic, and welcomes everyone to download

采用FPGA实现的DDS波形发生器源码，可以实现频率幅值变换、正弦波、方波、三角波输出，输出频率可达1MHz(FPGA implementation of the DDS waveform generator source frequency amplitude transform, sine wave, square wave, triangle wave output, the output frequency up to 1MHz)