EDA设计实验，用VHDL编写的数字时钟代码，能显示分，秒，小时。根据所设置的频率不同，能够调整时间快慢。...

一个用Verilog编写的编帧、解帧及码速匹配的程序，相当经典-Verilog prepared with a series of frames, frames and solutions yards speed matching procedures, rather classic!

DE2 S O P C 用硬件语言 描述地 开发板上测试 CLM模块 实现视频传输-DE2 SOPC LCM

关于Digilent Atlys Spartan-6 FPGA development board　audio ac97的讲解及具体应用的源码(Digilent Atlys Spartan-6 FPGA development board audio of ac97' s presentation as well as the specific application' s source code)

DE2-115 + D5M Camera to VGA PC

Verilog 经典实例，完整源码与大家分享-Verilog classic example of a complete source to share with you

完成十余卷积过程，简单方便，能够这样那样这样，sorry-Convolution process more than a decade to complete, simple and convenient, this can be done this way, sorry

由忆阻器机制设计蕴含逻辑，内含testbench仿真文件(Design implied logic by memristor mechanism, including testbench simulation file)

FPGA-based high-speed image acquisition system

uart串口传输的verilog RTL级源码，已通过仿真验证。文件主要包含发送、接受位处理，发送、接受字节帧处理，对学习串口通信的朋友很有帮助-uart serial transmission verilog RTL-level source code has been verified by simulation. File mainly contains the send, receive digital processing, sending, receiving bytes of frame processing, serial communications, a friend of learning helps

基于fpga的多功能数字时钟的实现，已经编译过了，绝对可行-fpga-baseed clock