EDA设计实验，用VHDL编写的数字时钟代码，能显示分，秒，小时。根据所设置的频率不同，能够调整时间快慢。...

verlog hdl无刷电机控制程序,已在modelsim仿真-verlog hdl brushless motor control procedures have been in ModelSim Simulation

单周期CPU自己课程大作业做的，亲测好用，verilog语言，适用vivado(Single cycle CPU course to do, pro - use, Verilog language, suitable for vivado)

自己编写的同步和异步FIFO的verilog代码，验证过，有可靠性(Verilog code of my own synchronous and asynchronous FIFO, verified,and reliable.)

带同步复位信号的二分频VHDL 程序-synchronous reset signal with the two-frequency VHDL procedures

运用vhdl程序设计语言进行ppm设计，ppm 设计在vhdl语言中非常常用，运用已经越来越广泛。-use vhdl program design language ppm design, vhdl ppm design in a very common language, has become increasingly widespread use.

自己写的键盘的扫描4乘4的键盘VHDL 很好用的-KEY SCAN VHDL

自己编写的AD7667的数据采集程序，因为之前没用过，首次写！

Altera board Mp3 project

FPGA实现串口发送 Verilog 语言(Serial reception FPGA Verilog language.)

基于FPGA设计的经典打砖块小游戏。游戏简单易玩。(FPGA design based on the classic Arkanoid game. Game easy to play.)