EDA设计实验，用VHDL编写的数字时钟代码，能显示分，秒，小时。根据所设置的频率不同，能够调整时间快慢。...

说明：  VHDL BISS,SSI,ENDAT2.2, ENCODER

UART的完整发送程序，包括完整的工程核源代码。-UART to send the complete procedure, including the complete source code of nuclear engineering.

说明：  Verilog实现液晶1602显示,学习使用(Verilog LCD1602)

this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural

i2c master ip for altera nios, add in qsys

I2C的VHDL源码，从机模式，编译通过。-I2C the VHDL source code, from the mode, the compiler through.

TIMING LEARNING -TIMING LEARNING

usb1.1的设备控制器IP核，是用verilog硬件描述语言写的-USB1.1 IP core for device control, written with hardware describing language of Verilog.

用Verilog编写的以太网控制器，可以使用，里面是全部verilog源码(Ethernet controller based on Verilog, can be used directly, all verilog files)

使用ISE软件实现OFDM通信系统的框架搭建，完成上板前的仿真工作(Realization of OFDM communication system with ISE software)