08EE06EDA 实验 4（VHDL 状态机设计_序列检测器）6/7/2008

verilg语言实现测频 及与stm32以fsmc通信方式进行通信(Verilg to achieve frequency measurement and communication with STM32 in FSMC communication mode)

16位并行乘法器源代码，booth2编码，二进制树拓扑结构(16bits parallel multiplier source code )

VHDL实现ALU的源代码，并且提供了一个详细的testbench！-ALU VHDL source code, and provide a detailed testbench!

CIC 补偿滤波器。采用两种方法来设计，一个是frequency sampling method。另一个是Equal Rippler Design Method。这是一个非常有用的matlab代码。(CIC compensation filter. Two ways to design a frequency sampling method. The other is an Equal Rippler Design Method. This is a very useful matlab code.)

Verilog HDL语言编写的汉明编码及解码器，附有时序仿真文件(Verilog HDL language encoding and decoding Hamming, with timing simulation file)

I am in need of some codes of HDL

user_logic_VGA_Controller，适合于DE2开发板，把这个文件夹放在工程目录之中，就可以在SOPC里直接添加VGA_Controller IP核了，很方便使用。-user_logic_VGA_Controller. suitable for Dictyophora development board, this folder on the project directory, it can be added directly SOPC Lane VGA_Controller IP core, very convenient to use.

自己今年的毕业设计DDS波形发生器,有正弦波,方波,三角波,锯齿波.-Their own design this year

decoder 2-4 digital core

该实验完成的功能是STM32与FPGA通信(The function of the experiment is STM32 and FPGA communication)