08EE06EDA 实验 4（VHDL 状态机设计_序列检测器）6/7/2008

用Verilog语言实现的FPGA UART独立收发模块 思路简单，代码简洁。在Lattice LFE3EA VERSA开发板上验证通过,编译器Lattice Diamond. 功能：串口收到数据后立即回传，此后每一秒串口数据+1再发送。(Using Verilog language independent of FPGA UART transceiver idea is simple, concise code. Development board in Lattice LFE3EA VERSA verified by the compiler Lattice Diamond. Features: Serial data is received immediately after the return, then every second serial port and then send the data+ 1.)

基于FPGA的PWM波生成程序，用于控制步进电机。(A PWM wave generater for driving stepper motor.)

vhdl 的testbench编写教程，英文ppt以及源码工程(Write tutorials, as well as English ppt Source of engineering vhdl testbench)

浙江大学体系结构实验代码 实现流水线的forwarding(Architecture, Zhejiang University Experimental code pipeline forwarding)

使用FPGA来控制DDS信号的产生，从而达到高频信号产生的目的。使用的DDS芯片为AD9852，在QuartusII下编写。(Using the FPGA to control the DDS signal generation, so as to achieve high-frequency signal generation purposes. Use of DDS chip AD9852, in the QuartusII prepared.)

包含32为乘法器的设计，用verilog语言实现，包括booth编码的实现，booth乘法器的实现，3_2压缩器的实现，4_2压缩器的实现，华伦斯树的实现，以及两个testbench文件用于测试。(Contains 32 multiplier design, verilog language, including booth encoding implementations, booth multiplier implementations, 3_2 compressor implementation 4_2 compressor to achieve and realize China Clarence tree, and two testbench file with the to the test.)

基于FPGA 16QAM解调verilog代码，(16QAMdemoluator veriliog)

串联型有源电力滤波器的 PSCAD仿真，能检测到谐波电压，本仿真的优势是能针对电压跌落或者升高进行自动补偿。(PSCAD simulation of Series type APF (Active Power Filter),this project can dectect the drop of voltage and compensates auomaticly.)

a code to display in VGA using VHDL lang

Verilog语言的流水灯设计程序，对初学者很有用。(Water lights Verilog language design program useful for beginners.)